prcm.h

omap3 linux 2.6 用nocc去除了冗余代码

/*
 * linux/include/asm-arm/arch-omap/prcm.h
 *
 * Access definitions for use in OMAP34XX clock and power management
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 *
 */

#define __ASM_ARM_ARCH_PRCM_H

/* Return Values of PRCM Lib API's */
#define PRCM_PASS	0
#define PRCM_FAIL	1

/* Definitions for enable/ disable */
#define PRCM_ENABLE	1
#define PRCM_DISABLE	0

#define PRCM_TRUE	1
#define PRCM_FALSE	0

/* Check accessibility or dont check accessibility*/
#define PRCM_ACCESS_CHK		1
#define PRCM_NO_ACCESS_CHK	0

/* IDLE METHOD */
#define PRCM_AUTO	1
#define PRCM_FORCE	2
#define PRCM_MANUAL	3

/* POWER DOMAIN STATES */
#define PRCM_OFF	0x0
#define PRCM_RET	0x1
#define PRCM_INACTIVE	0x2
#define PRCM_ON		0x3

/* Dpll resources */
#define DPLL_NO_AUTOIDLE                0x0
#define DPLL_AUTOIDLE                   0x1
#define DPLL_AUTOIDLE_BYPASS            0x5

/* memory and logic states */
#define MEMORY_OFF                      0x0
#define MEMORY_RET                      0x1
#define MEMORY_ON                       0x3
#define MEMORY_MAXLEVEL_DOMAINRET       0x2
#define MEMORY_MAXLEVEL_DOMAINON        0x4

#define LOGIC_OFF                       0x0
#define LOGIC_RET                       0x1
#define LOGIC_MAXLEVEL                  0x2


/* CLOCK STATE TRANSITIONS */
#define PRCM_NO_AUTO		0x0
#define PRCM_SWSUP_SLEEP	0x1
#define PRCM_SWSUP_WKUP		0x2
#define PRCM_HWSUP_AUTO		0x3

#define PRCM_FORCE_IDLE		0x0
#define PRCM_NO_IDLE		0x1
#define PRCM_SMART_IDLE		0x2
#define PRCM_SIDLEMODE_DONTCARE	0x3

#define PRCM_FORCE_STANDBY	0x0
#define PRCM_NO_STANDBY		0x1
#define PRCM_SMART_STANDBY	0x2
#define PRCM_MIDLEMODE_DONTCARE	0x3

/* Masks for standby, idle and auto idle modes */
#define PRCM_AUTO_IDLE_MASK	0x1
#define PRCM_IDLE_MASK		0x18
#define PRCM_STANDBY_MASK	0x3000

/* Offsets for standby, idle and auto idle modes */
#define PRCM_AUTO_IDLE_OFF	0x0
#define PRCM_IDLE_OFF		0x3
#define PRCM_STANDBY_OFF	0xC

/* Mask for setting wakeup dependency */
#define PRCM_WKDEP_EN_CORE	0x1
#define PRCM_WKDEP_EN_MPU	0x2
#define PRCM_WKDEP_EN_IVA2	0x4
#define PRCM_WKDEP_EN_WKUP	0x10
#define PRCM_WKDEP_EN_DSS	0x20
#define PRCM_WKDEP_EN_PER 	0x80

/* Mask for setting sleep dependency */
#define PRCM_SLEEPDEP_EN_CORE	0x1
#define PRCM_SLEEPDEP_EN_MPU	0x2
#define PRCM_SLEEPDEP_EN_IVA2	0x4

/* Mask for H/W supervised transitions L3, L4 and D2D CLKS */
#define CLK_D2D_HW_SUP_ENABLE	0x30
#define CLK_L4_HW_SUP_ENABLE	0xC
#define CLK_L3_HW_SUP_ENABLE	0x3

/* VDDs*/
#define PRCM_VDD1	1
#define PRCM_VDD2	2
#define PRCM_MAX_SYSC_REGS 30


/* OMAP Revisions */
#define AT_3430		1	/*3430 ES 1.0 */
#define AT_3430_ES2	2	/*3430 ES 2.0 */

/* Domains */
#define DOM_IVA2	1
#define DOM_MPU		2
#define DOM_CORE1	3
#define DOM_CORE2	4
#define DOM_SGX		5
#define DOM_WKUP	6
#define DOM_DSS		7
#define DOM_CAM		8
#define DOM_PER		9
#define DOM_EMU		10
#define DOM_NEON	11
#define DOM_CORE3	12
#define	DOM_USBHOST	13
#define PRCM_NUM_DOMAINS	13

/* DPLL's */
#define DPLL1_MPU	1
#define DPLL2_IVA2	2
#define DPLL3_CORE	3
#define DPLL4_PER	4
#define DPLL5_PER2	5
#define NO_OF_DPLL	5

/* PUT_DPLL_IN_BYPASS PARAMETERS */
#define LOW_POWER_STOP      1
#define LOW_POWER_BYPASS    5
#define FAST_RELOCK_BYPASS  6

/* DPLL dividers */
#define DPLL_M2 		0x0
#define DPLL_M2X2 		0x1
#define DPLL_M3X2		0x2
#define DPLL_M4X2		0x3
#define DPLL_M5X2		0x4
#define DPLL_M6X2		0x5
#define NO_DPLL_DIV		0x6

/* Device Type */
#define INITIATOR	1
#define TARGET		2
#define INIT_TAR	3

/* Clock Type */
#define FCLK	1
#define ICLK	2

/* Initiator masks for all domains */
#define IVA2_IMASK		0x1
#define MPU_IMASK		0x1
#define CORE2_IMASK		0x0
#define CORE1_IMASK		0x15
#define	CORE3_IMASK		0x0
#define SGX_IMASK		0x1
#define	USBHOST_IMASK		0x1
#define WKUP_IMASK		0x0
#define DSS_IMASK		0x1
#define CAM_IMASK		0x1
#define PER_IMASK		0x0
#define NEON_IMASK		0x1

/* Type of device IDs - Note that a particular device ID
 can be of multiple types*/
#define ID_DEV			0x0	/*Leaf node eg:uart */
#define ID_DPLL_OP		0x1	/*Dpll output */
#define ID_CLK_DIV		0x2	/*Clock has a divider */
#define ID_CLK_SRC		0x4	/*Source of the clock can be selected */

#define ID_CLK_PARENT		0xE1	/*Parent of some other clock */
#define ID_OPP			0xE2 	/*OPP*/
#define ID_MPU_DOM_STATE	0xE4	/*Mpu power domain state*/
#define ID_CORE_DOM_STATE	0xE8	/*Core power domain state*/
#define ID_SYSCONF		0xF0

#define ID_CONSTRAINT_CLK	0xF1	/* a clock rampup constraint */
#define ID_CONSTRAINT_OPP	0xF2	/* OPP constraint */
#define ID_CONSTRAINT_FREQ	0xF3	/* Frequnecy constraint */
#define ID_MEMORY_RES		0xF4	/* Memory resource */
#define ID_LOGIC_RES		0xF5	/* Logic resource */
#define ID_DPLL_RES		0xF6	/* Dpll resource */

/* DEVICE ID: bits 0-4 for Device bit position */
#define DEV_BIT_POS_SHIFT	0
#define DEV_BIT_POS_MASK	0x1F
/* DEVICE ID: bits 5-8 for domainid */
#define DOMAIN_ID_SHIFT		5
#define DOMAIN_ID_MASK		0xF
/* DEVICE ID: bits 9-10 for device type */
#define DEV_TYPE_SHIFT		9
#define DEV_TYPE_MASK		0x3
/* DEVICE ID: bits 11-13 for clk src*/
#define CLK_SRC_BIT_POS_SHIFT	11
#define CLK_SRC_BIT_POS_MASK	0x7
/* CLK ID: bits 14-18 for the clk number */
#define CLK_NO_POS		14
#define CLK_NO_MASK		0x1F
/* DPLL ID: bits 19-21  for the DPLL number */
#define DPLL_NO_POS 		19
#define DPLL_NO_MASK		0x7
/* DPLL ID: bits 22-24 for Divider */
#define DPLL_DIV_POS		22
#define DPLL_DIV_MASK		0x7
/* DEVICE ID/DPLL ID/CLOCK ID: bits 25-27 for ID type */
#define ID_TYPE_SHIFT		25
#define ID_TYPE_MASK		0x7
/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
#define OMAP_TYPE_SHIFT		28
#define OMAP_TYPE_MASK		0xF

/* Other IDs: bits 20-27 for ID type */
/* These IDs have bits 25,26,27 as 1 */
#define OTHER_ID_TYPE_SHIFT		20
#define OTHER_ID_TYPE_MASK		0xFF

/* OPP ID: bits: 0-4 for OPP number */
#define OPP_NO_POS		0
#define OPP_NO_MASK		0x1F
/* OPP ID: bits: 5-6 for VDD */
#define VDD_NO_POS		5
#define VDD_NO_MASK		0x3
/* COMMMON bits in DEVICE ID/DPLL ID/CLOCK ID */
/* Macros */
#define ID_DEV_BIT_POS(X)		((X & DEV_BIT_POS_MASK)<< DEV_BIT_POS_SHIFT)
#define ID_CLK_SRC_BIT_POS(X) 		((X & CLK_SRC_BIT_POS_MASK)<< CLK_SRC_BIT_POS_SHIFT)
#define ID_DOMAIN(X)			((X & DOMAIN_ID_MASK) << DOMAIN_ID_SHIFT)
#define ID_DEV_TYPE(X)			((X & DEV_TYPE_MASK) << DEV_TYPE_SHIFT)
#define ID_DPLL_NO(X)			((X & DPLL_NO_MASK) << DPLL_NO_POS)
#define ID_DPLL_DIV(X)			((X & DPLL_DIV_MASK) << DPLL_DIV_POS)
#define ID_CLK_NO(X)			((X & CLK_NO_MASK) << CLK_NO_POS)
#define ID_TYPE(X)			((X & ID_TYPE_MASK) << ID_TYPE_SHIFT)
#define OTHER_ID_TYPE(X)		((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
#define ID_ES(X)			((X & ES_TYPE_MASK) << ES_TYPE_SHIFT)
#define ID_OMAP(X)			((X & OMAP_TYPE_MASK) << OMAP_TYPE_SHIFT)
#define ID_OPP_NO(X)			((X & OPP_NO_MASK) << OPP_NO_POS)
#define ID_VDD(X)			((X & VDD_NO_MASK) << VDD_NO_POS)
#define DEV_BIT_POS(X)			((X >> DEV_BIT_POS_SHIFT) & DEV_BIT_POS_MASK)
#define CLK_SRC_BIT_POS(X)      	((X >> CLK_SRC_BIT_POS_SHIFT) & CLK_SRC_BIT_POS_MASK)
#define DOMAIN_ID(X)			((X >> DOMAIN_ID_SHIFT) & DOMAIN_ID_MASK)
#define DEV_TYPE(X)			((X >> DEV_TYPE_SHIFT) & DEV_TYPE_MASK)
#define OMAP(X)				((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
#define get_id_type(X)			((X >> ID_TYPE_SHIFT) & ID_TYPE_MASK)
#define get_other_id_type(X)		((X >> OTHER_ID_TYPE_SHIFT) & OTHER_ID_TYPE_MASK)
#define get_opp_no(X)			((X >> OPP_NO_POS) & OPP_NO_MASK)
#define get_vdd(X)			((X >> VDD_NO_POS) & VDD_NO_MASK)
#define get_addr(domainId,regId)	(dom_reg[domainId-1].regdef[regId].reg_addr)
#define get_val_bits(domainId,regId)	(dom_reg[domainId-1].regdef[regId].valid_bits)
#define get_addr_pll(dpll,regId)	(dpll_reg[dpll-1].regdef[regId].reg_addr)
#define get_val_bits_pll(dpll,regId)	(dpll_reg[dpll-1].regdef[regId].valid_bits)
#define get_idlest_lock_bit(dpll_id)	((dpll_id==DPLL4_PER)?0x2:0x1)
#define get_dpll_enbitmask(dpll_id)	((dpll_id==DPLL4_PER)?DPLL4_ENBIT_MASK:DPLL_ENBIT_MASK)
/* DEVICE ID's */
/* Devices in Core1 registers */
#define PRCM_SSI	(ID_OMAP(AT_3430) | ID_TYPE( (ID_DEV | ID_CLK_DIV)) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x0) | ID_CLK_NO(0x7))
#define PRCM_SDRC	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1))
#define PRCM_SDMA	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x2))
#define PRCM_D2D	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x3))
#define PRCM_HSOTG	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x4))


#define PRCM_OMAP_CTRL	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x6))
#define PRCM_MBOXES	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x7))
#define PRCM_FAC	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x8))
#define PRCM_MCBSP1	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
						| ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
						ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x9))
#define PRCM_MCBSP5	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
						| ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
						ID_CLK_SRC_BIT_POS(0x4) | ID_DEV_BIT_POS(0xA))
#define PRCM_GPT10	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
						| ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
						ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0xB))
#define PRCM_GPT11	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
						| ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
						ID_CLK_SRC_BIT_POS(0x7) | ID_DEV_BIT_POS(0xC))
#define PRCM_UART1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xD))
#define PRCM_UART2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xE))
#define PRCM_I2C1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xF))
#define PRCM_I2C2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x10))
#define PRCM_I2C3	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x11))
#define PRCM_MCSPI1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x12))
#define PRCM_MCSPI2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x13))
#define PRCM_MCSPI3	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x14))
#define PRCM_MCSPI4	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x15))
#define PRCM_HDQ	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x16))
#define PRCM_MSPRO	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x17))
#define PRCM_MMC1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x18))
#define PRCM_MMC2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x19))
#define PRCM_DES2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1A))
#define PRCM_SHA12	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1B))
#define PRCM_AES2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1C))
#define PRCM_ICR	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1D))
#define PRCM_MMC3	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1E))
#define PRCM_SMS	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(TARGET) | \
						ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x18))
#define PRCM_GPMC	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(TARGET) | \
						ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x19))
#define PRCM_MPU_INTC   (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(TARGET) | \
                                                ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1A))
#define PRCM_CORE1_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_CORE1))
/* Devices in Core2 registers */
#define PRCM_DES1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x0))
#define PRCM_SHA11	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x1))
#define PRCM_RNG	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x2))
#define PRCM_AES1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x3))
#define PRCM_PKA	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x4))

/* Devices in Core3 registers */
#define PRCM_CPEFUSE	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x0))
#define PRCM_TS		(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x1))
#define PRCM_USBTLL	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
						| ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x2))
/* Devices in SGX registers */
#define PRCM_SGX_ICLK	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |\
			ID_DEV_TYPE(INITIATOR) | ID_DOMAIN(DOM_SGX)\
			| ID_DEV_BIT_POS(0x0))
#define PRCM_SGX_FCLK	(ID_OMAP(AT_3430_ES2) |\
			ID_TYPE((ID_DEV | ID_CLK_DIV | ID_CLK_SRC))\
			| ID_DOMAIN(DOM_SGX) | ID_DEV_TYPE(TARGET) |\