prcm_34xx.c

omap3 linux 2.6 用nocc去除了冗余代码

/*
 * linux/arch/arm/mach-omap3/prcm_34xx.c
 *
 * OMAP 34xx Power Reset and Clock Management (PRCM) functions
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu/Rajendra Nayak/Pavan Chinnabhandar
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <asm/io.h>

#include <asm/arch/omap34xx.h>
#include <asm/arch/prcm.h>
#include <asm/arch/power_companion.h>
#include "prcm-regs.h"

/* #define DEBUG_PRCM 1 */
#  define DPRINTK(fmt, args...)

#define IOPAD_WKUP 1

/* Using 32K sync timer to generate delays in usecs */
#define OMAP_TIMER32K_SYNC_CR         (OMAP_TIMER32K_BASE + 0x10)
#define OMAP_TIMER32K_SYNC_CR_READ    (__raw_readl(OMAP_TIMER32K_SYNC_CR))

#define OMAP_MAX_32K_CR               0xFFFFFFFF


const u32 MAXLOOPCNT = 50;
const u32 MAXRETRIES = 5;

static int padconf_saved;

static unsigned int prcm_sleep_save[PRCM_SLEEP_SAVE_SIZE];
static struct gpmc_context gpmc_ctx;
static struct int_controller_context intc_context;
static struct control_module_context control_ctx;

extern void init_wakeupconfig(void);
extern void uart_padconf_control(void);
extern void setup_board_wakeup_source(u32);

/* Table to store domain registers */
struct domain_registers dom_reg[PRCM_NUM_DOMAINS] = {
	{
/*  DEBUG_ONLY		valid_bits   reg_addr				----- */

		/* 0x00 : IVA2 domain */
		{
			{0x1,		&CM_FCLKEN_IVA2},
			{0,		0},
			{0x1,		&CM_IDLEST_IVA2},
			{0,		0},
			{0,		0},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_IVA2},
			{0x1,		&CM_CLKSTST_IVA2},
			{0xFF0F0F,	&PM_PWSTCTRL_IVA2},
			{0x100FF7,	&PM_PWSTST_IVA2},
			{0xFF7,		&PM_PREPWSTST_IVA2},
			{0,		0},
			{0x3F0F,	&RM_RSTST_IVA2},
		}
	},
	{
		/* 0x01 : MPU domain */
		{
			{0,		0},
			{0,		0},
			{0x1,		&CM_IDLEST_MPU},
			{0,		0},
			{0,		0},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_MPU},
			{0x1,		&CM_CLKSTST_MPU},
			{0x3010F,	&PM_PWSTCTRL_MPU},
			{0x1000C7,	&PM_PWSTST_MPU},
			{0xC7,		&PM_PREPWSTST_MPU},
			{0,		0},
			{0x80F,		&RM_RSTST_MPU},
		}
	},
	{
		/* 0x02 : CORE1 */
		{
			{0x43FFFE01,	&CM_FCLKEN1_CORE},
			{0x7FFFFED3,	&CM_ICLKEN1_CORE},
			{0x7FFFFFF7,	&CM_IDLEST1_CORE},
			{0x7FFFFED1,	&CM_AUTOIDLE1_CORE},
			{0x433FFE10,	&PM_WKEN1_CORE},
			{0x433FFE10,	&PM_WKST1_CORE},
			{0x0F,		&CM_CLKSTCTRL_CORE},
			{0x3, 		&CM_CLKSTST_CORE},
			{0xF031F,	&PM_PWSTCTRL_CORE},
			{0x1000F7,	&PM_PWSTST_CORE},
			{0xF7,		&PM_PREPWSTST_CORE},
			{0xC0,		&CM_CLKSEL_CORE},
			{0x7,		&RM_RSTST_CORE},
		}
	},
	{
		/* 0x03 : CORE2 */
		{
			{0,		0},
			{0x1F,		&CM_ICLKEN2_CORE},
			{0x1F,		&CM_IDLEST2_CORE},
			{0x1F,		&CM_AUTOIDLE2_CORE},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	},
	{
		/* 0x04 : GFX OR SGX */
		{
			{0x2,		&CM_FCLKEN_SGX},
			{0x1,		&CM_ICLKEN_SGX},
			{0x1,		&CM_IDLEST_SGX},
			{0, 		0},
			{0, 		0},
			{0, 		0},
			{0x3,		&CM_CLKSTCTRL_SGX},
			{0x1,		&CM_CLKSTST_SGX},
			{0x30107,	&PM_PWSTCTRL_SGX},
			{0x100003,	&PM_PWSTST_SGX},
			{0x3,		&PM_PREPWSTST_SGX},
			{0, 		0},
			{0xF,		&RM_RSTST_SGX},
		}
	},
	{
		/* 0x05 : WKUP */
		{
			{0x2E9,		&CM_FCLKEN_WKUP},
			{0x23F,		&CM_ICLKEN_WKUP},
			{0x2FF,		&CM_IDLEST_WKUP},
			{0x23F,		&CM_AUTOIDLE_WKUP},
			{0x3CB,		&PM_WKEN_WKUP},
			{0x3CB,		&PM_WKST_WKUP},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0x7F,		&CM_CLKSEL_WKUP},
			{0,		0},
		}
	},
	{
		/* 0x06 : DSS */
		{
			{0x7,		&CM_FCLKEN_DSS},
			{0x1,		&CM_ICLKEN_DSS},
			{0x3,		&CM_IDLEST_DSS},
			{0x1,		&CM_AUTOIDLE_DSS},
			{0x1,		&PM_WKEN_DSS},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_DSS},
			{0x1,		&CM_CLKSTST_DSS},
			{0x30107,	&PM_PWSTCTRL_DSS},
			{0x100003,	&PM_PWSTST_DSS},
			{0x3,		&PM_PREPWSTST_DSS},
			{0,		0},
			{0xF,		&RM_RSTST_DSS},
		}
	},
	{
		/* 0x07 : CAM */
		{
			{0x3,		&CM_FCLKEN_CAM},
			{0x1,		&CM_ICLKEN_CAM},
			{0x1,		&CM_IDLEST_CAM},
			{0x1,		&CM_AUTOIDLE_CAM},
			{0,		0},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_CAM},
			{0x1,		&CM_CLKSTST_CAM},
			{0x30107,	&PM_PWSTCTRL_CAM},
			{0x100003,	&PM_PWSTST_CAM},
			{0x3,		&PM_PREPWSTST_CAM},
			{0,		0},
			{0xF,		&RM_RSTST_CAM},
		}
	},
	{
		/* 0x08 : PER */
		{
			{0x3FFFF,	&CM_FCLKEN_PER},
			{0x3FFFF,	&CM_ICLKEN_PER},
			{0x3FFFF,	&CM_IDLEST_PER},
			{0x3FFFF,	&CM_AUTOIDLE_PER},
			{0x3EFFF,	&PM_WKEN_PER},
			{0x3EFFF,	&PM_WKST_PER},
			{0x3,		&CM_CLKSTCTRL_PER},
			{0x1,		&CM_CLKSTST_PER},
			{0x30107,	&PM_PWSTCTRL_PER},
			{0x100003,	&PM_PWSTST_PER},
			{0x3,		&PM_PREPWSTST_PER},
			{0xFF,		&CM_CLKSEL_PER},
			{0xF,		&RM_RSTST_PER},
			}
	},
	{
		/* 0x09 : EMU */
		{
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_EMU},
			{0x1,		&CM_CLKSTST_EMU},
			{0,		0},
			{0x100003,	&PM_PWSTST_EMU},
			{0,		0},
			{0,		0},
			{0x7,		&RM_RSTST_EMU},
		}
	},
	{
		/* 0x0A : NEON */
		{
			{0,		0},
			{0,		0},
			{0x1,		&CM_IDLEST_NEON},
			{0,		0},
			{0,		0},
			{0,		0},
			{0x3,		&CM_CLKSTCTRL_NEON},
			{0,		0},
			{0x7,		&PM_PWSTCTRL_NEON},
			{0x100003,	&PM_PWSTST_NEON},
			{0x3,		&PM_PREPWSTST_NEON},
			{0,		0},
			{0xF,		&RM_RSTST_NEON},
		}
	},
	{
		/* 0x0B : CORE3 */
		{
			{0x7,		&CM_FCLKEN3_CORE},
			{0x4,		&CM_ICLKEN3_CORE},
			{0x5,		&CM_IDLEST3_CORE},
			{0x4,		&CM_AUTOIDLE3_CORE},
			{0x4,		&PM_WKEN3_CORE},
			{0x4,		&PM_WKST3_CORE},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	},
	{
		/* 0x0C : USBHOST */
		{
			{0x3,		&CM_FCLKEN_USBHOST},
			{0x1,		&CM_ICLKEN_USBHOST},
			{0x3,		&CM_IDLEST_USBHOST},
			{0x1,		&CM_AUTOIDLE_USBHOST},
			{0x1,		&PM_WKEN_USBHOST},
			{0x1,		&PM_WKST_USBHOST},
			{0x3,		&CM_CLKSTCTRL_USBHOST},
			{0x1,		&CM_CLKSTST_USBHOST},
			{0x30117,	&PM_PWSTCTRL_USBHOST},
			{0x100003,	&PM_PWSTST_USBHOST},
			{0x3,		&PM_PREPWSTST_USBHOST},
			{0,		0},
			{0xF,		&RM_RSTST_USBHOST},
		}
	},
};

/* Table to store DPLL registers */
struct dpll_registers dpll_reg[NO_OF_DPLL] = {
	{
		/* DPLL1_MPU */
		{
			{0xFFFFFF0F,	&CM_CLKEN_PLL_MPU},
			{0x7,		&CM_AUTOIDLE_PLL_MPU},
			{0xFFF800FF,	&CM_CLKSEL1_PLL_MPU},
			{0,		&CM_IDLEST_PLL_MPU},
			{0xFFFFFFE0,	&CM_CLKSEL2_PLL_MPU},
			{0xFFFFFFE0,	&CM_CLKSEL2_PLL_MPU},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	},
	{
		/* DPLL2_IVA2 */
		{
			{0xFFFFFF0F,	&CM_CLKEN_PLL_IVA2},
			{0x7,		&CM_AUTOIDLE_PLL_IVA2},
			{0xFFF800FF,	&CM_CLKSEL1_PLL_IVA2},
			{0,		&CM_IDLEST_PLL_IVA2},
			{0xFFFFFFE0,	&CM_CLKSEL2_PLL_IVA2},
			{0xFFFFFFE0,	&CM_CLKSEL2_PLL_IVA2},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	},
	{
		/* DPLL3_CORE */
		{
			{0xFFFFFF0F,	&CM_CLKEN_PLL},
			{0x7,		&CM_AUTOIDLE_PLL},
			{0xF800FFFF,	&CM_CLKSEL1_PLL},
			{0,		&CM_IDLEST_CKGEN},
			{0x07FFFFFF,	&CM_CLKSEL1_PLL},
			{0x07FFFFFF,	&CM_CLKSEL1_PLL},
			{0xFFE0FFFF,	&CM_CLKSEL1_EMU},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	},
	{
		/* DPLL4_PER */
		{
			{0xFF0FFFFF,	&CM_CLKEN_PLL},
			{0x38,		&CM_AUTOIDLE_PLL},
			{0xFFF800FF,	&CM_CLKSEL2_PLL},
			{0,		&CM_IDLEST_CKGEN},
			{0xFFFFFFE0,	&CM_CLKSEL3_PLL},
			{0xFFFFFFE0,	&CM_CLKSEL3_PLL},
			{0xFFFFE0FF,	&CM_CLKSEL_DSS},
			{0xFFFFFFE0,	&CM_CLKSEL_DSS},
			{0xFFFFFFE0,	&CM_CLKSEL_CAM},
			{0xE0FFFFFF,	&CM_CLKSEL1_EMU},
		}
	},
	{
		/* DPLL5_PER2 */
		{
			{0xFFFFFF0F,	&CM_CLKEN2_PLL},
			{0x7,		&CM_AUTOIDLE2_PLL},
			{0xFFF800FF,	&CM_CLKSEL4_PLL},
			{0,		&CM_IDLEST2_CKGEN},
			{0xFFFFFFE0,	&CM_CLKSEL5_PLL},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
			{0,		0},
		}
	}
};

/* Table to store clksel registers for various clocks */
struct reg_def clksel_reg[PRCM_NO_OF_CLKS] = {
	{0x3,		&CM_CLKSEL_CORE},		/* L3_ICLK */
	{0xC,		&CM_CLKSEL_CORE},		/* L4_ICLK */
	{0x6,		&CM_CLKSEL_WKUP},		/* RM_ICLK */
	{0x00,		NULL},
	{0x38,		&CM_CLKOUT_CTRL},		/* SYS_CLOCKOUT2 */
	{0x7,		&CM_CLKSEL_SGX},		/* SGX_L3_FCLK */
	{0xF00,		&CM_CLKSEL_CORE},		/* SSI */
	{0x180000,	&CM_CLKSEL1_PLL_MPU},		/* DPLL1_FCLK */
	{0x180000,	&CM_CLKSEL1_PLL_IVA2},		/* DPLL2_FCLK */
	{0x78,		&CM_CLKSEL_WKUP},		/* USIM_FCLK */
};

/* Tables to store sysconfig registers for each PRCM ID */
/* CORE */
struct sysconf_reg sysc_reg_core1[] = {
	{PRCM_SSI,		&PRCM_SSI_SYSCONFIG},
	{PRCM_SDRC,		&PRCM_SDRC_SYSCONFIG},
	{PRCM_SDMA,		&PRCM_SDMA_SYSCONFIG},
	{PRCM_HSOTG,		&PRCM_HSOTG_SYSCONFIG},
	{PRCM_OMAP_CTRL,	&PRCM_OMAP_CTRL_SYSCONFIG},
	{PRCM_MBOXES,		&PRCM_MBOXES_SYSCONFIG},
	{PRCM_MCBSP1,		&PRCM_MCBSP1_SYSCONFIG},
	{PRCM_MCBSP5,		&PRCM_MCBSP5_SYSCONFIG},
	{PRCM_GPT10,		&PRCM_GPT10_SYSCONFIG},
	{PRCM_GPT11,		&PRCM_GPT11_SYSCONFIG},
	{PRCM_UART1,		&PRCM_UART1_SYSCONFIG},
	{PRCM_UART2,		&PRCM_UART2_SYSCONFIG},
	{PRCM_I2C1,		&PRCM_I2C1_SYSCONFIG},
	{PRCM_I2C2,		&PRCM_I2C2_SYSCONFIG},
	{PRCM_I2C3,		&PRCM_I2C3_SYSCONFIG},
	{PRCM_MCSPI1,		&PRCM_MCSPI1_SYSCONFIG},
	{PRCM_MCSPI2,		&PRCM_MCSPI2_SYSCONFIG},
	{PRCM_MCSPI3,		&PRCM_MCSPI3_SYSCONFIG},
	{PRCM_MCSPI4,		&PRCM_MCSPI4_SYSCONFIG},
	{PRCM_HDQ,		&PRCM_HDQ_SYSCONFIG},
	{PRCM_MMC1,		&PRCM_MMC1_SYSCONFIG},
	{PRCM_MMC2,		&PRCM_MMC2_SYSCONFIG},
	{PRCM_SMS,		&PRCM_SMS_SYSCONFIG},
	{PRCM_GPMC,		&PRCM_GPMC_SYSCONFIG},
	{PRCM_MPU_INTC,		&PRCM_MPU_INTC_SYSCONFIG},
	{PRCM_MMC3,		&PRCM_MMC3_SYSCONFIG},
	{0x0,			0x0},
};

/* WKUP */
struct sysconf_reg sysc_reg_wkup[] = {
	{PRCM_GPIO1,	&PRCM_GPIO1_SYSCONFIG},
	{PRCM_GPT1,	&PRCM_GPT1_SYSCONFIG},
	{PRCM_GPT12,	&PRCM_GPT12_SYSCONFIG},
	{PRCM_WDT2,	&PRCM_WDT2_SYSCONFIG},
	{0x0,		0x0},
};

/* DSS */
struct sysconf_reg sysc_reg_dss[] = {
	{PRCM_DSS,	&PRCM_DSS_SYSCONFIG},
	{PRCM_DISPC,	&PRCM_DISPC_SYSCONFIG},
	{PRCM_RFBI,	&PRCM_RFBI_SYSCONFIG},
	{0x0,		0x0},
};

/* CAM */
struct sysconf_reg sysc_reg_cam[] = {
	{PRCM_CAM,	&PRCM_CAM_SYSCONFIG},
	{PRCM_CSIA,	&PRCM_CSIA_SYSCONFIG},
	{PRCM_CSIB,	&PRCM_CSIB_SYSCONFIG},
	{PRCM_MMU,	&PRCM_MMU_SYSCONFIG},
	{0x0,		0x0},
};

/* PER */
struct sysconf_reg sysc_reg_per[] = {
	{PRCM_MCBSP2,	&PRCM_MCBSP2_SYSCONFIG},
	{PRCM_MCBSP3,	&PRCM_MCBSP3_SYSCONFIG},
	{PRCM_MCBSP4,	&PRCM_MCBSP4_SYSCONFIG},
	{PRCM_GPT2,	&PRCM_GPT2_SYSCONFIG},
	{PRCM_GPT3,	&PRCM_GPT3_SYSCONFIG},
	{PRCM_GPT4,	&PRCM_GPT4_SYSCONFIG},
	{PRCM_GPT5,	&PRCM_GPT5_SYSCONFIG},
	{PRCM_GPT6,	&PRCM_GPT6_SYSCONFIG},
	{PRCM_GPT7,	&PRCM_GPT7_SYSCONFIG},