prcm-debug.c

来自「omap3 linux 2.6 用nocc去除了冗余代码」· C语言 代码 · 共 2,079 行 · 第 1/5 页

		goto revert1;
	}
	/* Get the revised rates once they are in bypass  */
	prcm_get_dpll_rate(PRCM_DPLL1_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL1_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL2_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL2_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M3X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M3X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DSS, &dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL5_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL5_M2_CLK = %d\n", dpll_rate);
	DPRINTK1("PRCM_DSS = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_CAM, &dpll_rate);
	DPRINTK1("PRCM_CAM = %d\n", dpll_rate);

	/* Configure M=651,N=19,FREQ=0x3,M2=2 for DPLL1*/
	if (prcm_configure_dpll(DPLL1_MPU, 0x28B, 0x13, 0x3) != PRCM_PASS) {
		printk("1 - Unable to configure DPLL1\n");
		goto revert1;
	}
	if (prcm_configure_dpll(DPLL2_IVA2, 0x203, 0x16, 0x3) != PRCM_PASS) {
		printk(KERN_ERR"2 - Unable to configure DPLL2\n");
		goto revert1;
	}
	if (prcm_configure_dpll(DPLL5_PER2, 0x4B, 0xB, 0x6) != PRCM_PASS) {
		printk(KERN_ERR"3 - Unable to configure DPLL5\n");
		goto revert1;
	}
	if (prcm_configure_dpll_divider(PRCM_DPLL1_M2X2_CLK, 0x2)
				!= PRCM_PASS) {
		printk(KERN_ERR"Unable to configure PRCM_DPLL1_M2X2_CLK\n");
		goto revert1;
	}
	if (prcm_configure_dpll_divider(PRCM_DPLL2_M2X2_CLK, 0x2)
				!= PRCM_PASS) {
		printk(KERN_ERR"Unable to configure PRCM_DPLL2_M2X2_CLK\n");
		goto revert1;
	}

	/* Re-enable DPLL1/DPLL2/DPLL5 */
	if (prcm_enable_dpll(DPLL1_MPU) != PRCM_PASS) {
		DPRINTK1("DPLL1 enable failed\n");
		ret = -2;
		goto revert1;
	}
	if (prcm_enable_dpll(DPLL2_IVA2) != PRCM_PASS) {
		DPRINTK1("DPLL2 enable failed\n");
		return -1;
	}
	if (prcm_enable_dpll(DPLL5_PER2) != PRCM_PASS) {
		DPRINTK1("DPLL5 enable failed\n");
		return -1;
	}

	/* Get the new rates  */
	prcm_get_dpll_rate(PRCM_DPLL1_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL1_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL2_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL2_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M3X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M3X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DSS, &dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL5_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL5_M2_CLK = %d\n", dpll_rate);
	DPRINTK1("PRCM_DSS = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_CAM, &dpll_rate);
	DPRINTK1("PRCM_CAM = %d\n", dpll_rate);

	if (prcm_put_dpll_in_bypass(DPLL2_IVA2, LOW_POWER_BYPASS)
							!= PRCM_PASS) {
		DPRINTK1("Unable to put DPLL2 in Bypass\n");
		return -1;
	}
	/* Configure M2=1 for DPLL2 */
	if (prcm_configure_dpll_divider(PRCM_DPLL2_M2X2_CLK, 0x1)
				!= PRCM_PASS) {
		printk(KERN_INFO"a - Unable to configure PRCM_DPLL2_M2X2_CLK"
				"\n");
		ret = -2;
		goto revert1;
	}
	/* Need to replace the old values back */
	if (prcm_put_dpll_in_bypass(DPLL1_MPU, LOW_POWER_BYPASS)
							!= PRCM_PASS) {
		DPRINTK1("Unable to put DPLL1 in Bypass\n");
		return -1;
	}
	if (prcm_configure_dpll_divider(PRCM_DPLL1_M2X2_CLK, 0x1)
				!= PRCM_PASS) {
		printk(KERN_ERR"2a - Unable to configure PRCM_DPLL1_M2X2_CLK"
				"\n");
		goto revert0;
	}

	/* Re-enable DPLL1/DPLL2 */
	if (prcm_enable_dpll(DPLL1_MPU) != PRCM_PASS) {
		DPRINTK1("a - DPLL1 enable failed\n");
		ret = -2;
		goto revert1;
	}
	if (prcm_enable_dpll(DPLL2_IVA2) != PRCM_PASS) {
		DPRINTK1("a - DPLL2 enable failed\n");
		return -1;
	}
	if (prcm_enable_dpll(DPLL5_PER2) != PRCM_PASS) {
		DPRINTK1("DPLL5 enable failed\n");
		return -1;
	}
	/* Re-enable DPLL5 autoidle */
	CM_AUTOIDLE2_PLL = 0x1;
	return 0;

revert1:
	ret = prcm_enable_dpll(DPLL2_IVA2);
	if (ret != PRCM_PASS)
		DPRINTK1("a - DPLL2 enable failed\n");

	if (ret == -2)
		return -1;

revert0:
	if (prcm_enable_dpll(DPLL1_MPU))
		DPRINTK1("a - DPLL1 enable failed\n");

	return -1;
}
EXPORT_SYMBOL(dpllapi_test);

int voltage_scaling_tst(u32 target_opp_id, u32 current_opp_id)
{
	u32 curr_opp_no, target_opp_no;
	u32 vdd;
	struct clk *p_vdd1_clk;
	struct clk *p_vdd2_clk;
	u32 valid_rate;

	DPRINTK1("\n");

	vdd = get_vdd(target_opp_id);

	p_vdd1_clk = clk_get(NULL, "virt_vdd1_prcm_set");
	p_vdd2_clk = clk_get(NULL, "virt_vdd2_prcm_set");
	curr_opp_no = current_opp_id & OPP_NO_MASK;
	target_opp_no = target_opp_id & OPP_NO_MASK;

	if (vdd == PRCM_VDD1) {
		DPRINTK1("Before - VDD1 rate is %lu\n",
				clk_get_rate(p_vdd1_clk));
		DPRINTK1("Before - BogoMIPS\t: %lu.%02lu\n",
		   loops_per_jiffy / (500000/HZ),
		   (loops_per_jiffy / (5000/HZ)) % 100);
		if (scale_voltage_then_frequency) {
			prcm_do_voltage_scaling(target_opp_id, current_opp_id);
			valid_rate = clk_round_rate(p_vdd1_clk,
				round_rate_vdd1[target_opp_no-1]);
			p_vdd1_clk->set_rate(p_vdd1_clk, valid_rate);
		} else {
			valid_rate = clk_round_rate(p_vdd1_clk,
					round_rate_vdd1[target_opp_no-1]);
			p_vdd1_clk->set_rate(p_vdd1_clk, valid_rate);
			prcm_do_voltage_scaling(target_opp_id, current_opp_id);
		}
		DPRINTK1("After - VDD1 rate is %lu\n",
				clk_get_rate(p_vdd1_clk));
		DPRINTK1("After - BogoMIPS\t: %lu.%02lu\n",
		   loops_per_jiffy / (500000/HZ),
		   (loops_per_jiffy / (5000/HZ)) % 100);

	} else if (vdd == PRCM_VDD2) {
		DPRINTK1("Before - VDD2 rate is %lu\n",
				clk_get_rate(p_vdd2_clk));
		if (scale_voltage_then_frequency) {
			prcm_do_voltage_scaling(target_opp_id, current_opp_id);
			valid_rate = clk_round_rate(p_vdd2_clk,
					round_rate_vdd2[target_opp_no-1]);
			p_vdd2_clk->set_rate(p_vdd2_clk, valid_rate);
		} else {
			valid_rate = clk_round_rate(p_vdd2_clk,
					round_rate_vdd2[target_opp_no-1]);
			p_vdd2_clk->set_rate(p_vdd2_clk, valid_rate);
			prcm_do_voltage_scaling(target_opp_id, current_opp_id);
		}
		DPRINTK1("After - VDD2 rate is %lu\n",
				clk_get_rate(p_vdd2_clk));
	}
	return 0;
}

int voltage_scaling_set_of_test (void)
{
	int i, e = 0;

	DPRINTK1("#### Start of Voltage Scaling tests \n");

	ssleep(5);
	e |= voltage_scaling_tst(PRCM_VDD1_OPP1, current_vdd1_opp);

	ssleep(5);
	e |= voltage_scaling_tst(PRCM_VDD1_OPP2, PRCM_VDD1_OPP1);

	ssleep(5);
	e |= voltage_scaling_tst(PRCM_VDD1_OPP3, PRCM_VDD1_OPP2);

	ssleep(5);
	e |= voltage_scaling_tst(PRCM_VDD1_OPP4, PRCM_VDD1_OPP3);

	ssleep(5);
	e |= voltage_scaling_tst(PRCM_VDD1_OPP5, PRCM_VDD1_OPP4);
	if (current_vdd1_opp != PRCM_VDD1_OPP5) {
		ssleep(5);
		e |= voltage_scaling_tst(current_vdd1_opp, PRCM_VDD1_OPP5);
	}
	for (i = 0; i < 2; i++) {
		ssleep(5);
		e |= voltage_scaling_tst(PRCM_VDD2_OPP2, current_vdd2_opp);
		ssleep(5);
		e |= voltage_scaling_tst(current_vdd2_opp, PRCM_VDD2_OPP2);
		if (e)
			break;
	}

	DPRINTK1("#### End of Voltage Scaling tests \n");
	return e;
}
EXPORT_SYMBOL(voltage_scaling_set_of_test);

int frequency_scaling_test(void)
{
	u32 dpll_rate;

	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);

	if (prcm_do_frequency_scaling(PRCM_VDD2_OPP2, PRCM_VDD2_OPP3)
							!= PRCM_PASS) {
		DPRINTK1("Error in prcm_do_frequency_scaling for VDD2\n");
		return -1;
	} else
		DPRINTK1("\nDone Freq scaling DONE VDD2.... \n\n");

	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);

	if (prcm_do_frequency_scaling(PRCM_VDD2_OPP3, PRCM_VDD2_OPP2)
							!= PRCM_PASS) {
		DPRINTK1("Error in prcm_do_frequency_scaling for VDD2\n");
		return -1;
	} else
		DPRINTK1("\nDone Freq scaling DONE VDD2.... \n\n");

	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);

	return 0;
}
EXPORT_SYMBOL(frequency_scaling_test);

void constraint_test(unsigned int co_type, unsigned long target_value,
			int action)
{
	switch (co_type) {
	case RES_LATENCY_CO:
		if (action == REQUEST_CO) {
			co_latency = constraint_get("test",
					&cnstr_id_lat);
			constraint_set(co_latency, target_value);
		} else if (action == RELEASE_CO) {
			constraint_remove(co_latency);
			constraint_put(co_latency);
		}
		break;
	case PRCM_VDD1_CONSTRAINT:
		if (action == REQUEST_CO) {
			co_opp = constraint_get("test", &cnstr_id_vdd1);
			constraint_register_pre_notification(co_opp,
					&nb_test_pre, MAX_VDD1_OPP+1);
			constraint_register_post_notification(co_opp,
					&nb_test_post, MAX_VDD1_OPP+1);
			constraint_set(co_opp, target_value);
		} else if (action == RELEASE_CO) {
			constraint_remove(co_opp);
			constraint_unregister_pre_notification(co_opp,
					&nb_test_pre, MAX_VDD1_OPP+1);
			constraint_unregister_post_notification(co_opp,
					&nb_test_post, MAX_VDD1_OPP+1);
			constraint_put(co_opp);
		}
		break;
	case PRCM_VDD2_CONSTRAINT:
		if (action == REQUEST_CO) {
			co_opp = constraint_get("test", &cnstr_id_vdd2);
			constraint_register_pre_notification(co_opp,
					&nb_test_pre, MAX_VDD2_OPP+1);
			constraint_register_post_notification(co_opp,
					&nb_test_post, MAX_VDD2_OPP+1);
			constraint_set(co_opp, target_value);
		} else if (action == RELEASE_CO) {
			constraint_remove(co_opp);
			constraint_unregister_pre_notification(co_opp,
					&nb_test_pre, MAX_VDD2_OPP+1);
			constraint_unregister_post_notification(co_opp,
					&nb_test_post, MAX_VDD2_OPP+1);
			constraint_put(co_opp);
		}
		break;
	case PRCM_ARMFREQ_CONSTRAINT:
		if (action == REQUEST_CO) {
			co_opp = constraint_get("test", &cnstr_id_arm);
			constraint_register_pre_notification(co_opp,
					&nb_test_pre, -1);
			constraint_register_post_notification(co_opp,
					&nb_test_post, -1);
			constraint_set(co_opp, target_value);
		} else if (action == RELEASE_CO) {
			constraint_remove(co_opp);
			constraint_unregister_pre_notification(co_opp,
					&nb_test_pre, -1);
			constraint_unregister_post_notification(co_opp,
					&nb_test_post, -1);
			constraint_put(co_opp);
		}
		break;
	case PRCM_DSPFREQ_CONSTRAINT:
		if (action == REQUEST_CO) {
			co_opp = constraint_get("test", &cnstr_id_dsp);
			constraint_register_pre_notification(co_opp,
					&nb_test_pre, -1);
			constraint_register_post_notification(co_opp,
					&nb_test_post, -1);
			constraint_set(co_opp, target_value);
		} else if (action == RELEASE_CO) {
			constraint_remove(co_opp);
			constraint_unregister_pre_notification(co_opp,
					&nb_test_pre, -1);
			constraint_unregister_post_notification(co_opp,
					&nb_test_post, -1);
			constraint_put(co_opp);
		}
		break;
	default:
		break;
	}
	return;
}
EXPORT_SYMBOL(constraint_test);

int resource_test_1(const char *usr_name, char *name);
int resource_test_2(char *name);
int resource_test_3(char *name);
int resource_notification_test(const char *usr_name, char *name);
void turn_power_domains_on(u8 domainid);
int test_logical_resource(char *name);

struct device_driver cameraisp_drv = {
	.name =  "cameraisp",
};

struct device cameraisp_dev = {
	.driver = &cameraisp_drv,
};

struct device_driver sgx_drv = {
	.name =  "sgx",
};

struct device sgx_dev = {
	.driver = &sgx_drv,
};

struct device dev_1 = {
	.driver = &sgx_drv,
};

struct device dev_2 = {
	.driver = &sgx_drv,
};

struct device dev_3 = {
	.driver = &sgx_drv,
};

struct device dev_4 = {
	.driver = &sgx_drv,
};
struct device logical_res;

int resource_test(void)
{
	u32 camf, cami;
	int ret;
	u32 sgxf, sgxi;
	/* Save clock registers */
	sgxf = CM_FCLKEN_SGX;
	sgxi = CM_ICLKEN_SGX;
	CM_FCLKEN_SGX   = 0x0;
	CM_ICLKEN_SGX   = 0x0;
	camf = CM_FCLKEN_CAM;
	cami = CM_ICLKEN_CAM;
	/* Disable the clocks */
	CM_FCLKEN_CAM   = 0x0;
	CM_ICLKEN_CAM   = 0x0;

	ret = resource_test_1("graphics", "sgx");
	if (ret != 0)
		goto test_fail;
	ret = resource_test_2("sgx");
	if (ret != 0)