prcm-debug.c

来自「omap3 linux 2.6 用nocc去除了冗余代码」· C语言 代码 · 共 2,079 行 · 第 1/5 页

		PM_WKDEP_USBHOST |= (1 << 1);
		PM_WKDEP_DSS |= (1 << 1);
		PM_WKDEP_PER |= (1 << 1);
		PM_WKDEP_NEON |= (1 << 1);

		if (tries == 0) {
			/* Prog the domains to ON */
			DPRINTK1("Programming CAM/SGX/DSS/PER to ON using AUTO"
					" mode\n");
			ret |= prcm_set_power_state(DOM_CAM, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_SGX, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_USBHOST, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_DSS, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_PER, PRCM_AUTO,
							PRCM_ON);
			if (ret) {
				printk(KERN_ERR"Error in setting the power "
					"states\n");
				goto revert;
			}
		}

		/* Program MPU for Ret and execute WFI */
		DPRINTK1("Programming MPU to go to retention using AUTO mode"
				"\n");
		prcm_set_power_state(DOM_MPU, PRCM_AUTO, PRCM_RET);
		/* wfi */
		execute_idle();

		if (tries > 0) {
			/* Prog the domains to ON */
			DPRINTK1("Programming CAM/SGX/DSS/PER to ON using AUTO"
					" mode\n");
			ret |= prcm_set_power_state(DOM_CAM, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_SGX, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_USBHOST, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_DSS, PRCM_AUTO,
							PRCM_ON);
			ret |= prcm_set_power_state(DOM_PER, PRCM_AUTO,
							PRCM_ON);
			if (ret) {
				printk(KERN_ERR"Error in setting the power "
						"states \n");
				goto revert;
			}
		}

		/* Check for the previous MPU state */
		DPRINTK1("Previous MPU state = %x\n", PM_PREPWSTST_MPU);
		prcm_get_power_domain_state(DOM_CAM, &state);
		DPRINTK1("Current  CAM state = %x\n", state);
		prcm_get_power_domain_state(DOM_SGX, &state);
		DPRINTK1("Current  SGX state = %x\n", state);
		prcm_get_power_domain_state(DOM_USBHOST, &state);
		DPRINTK1("Current  USBHOST state = %x\n", state);
		prcm_get_power_domain_state(DOM_DSS, &state);
		DPRINTK1("Current  DSS state = %x\n", state);
		prcm_get_power_domain_state(DOM_PER, &state);
		DPRINTK1("Current  PER state = %x\n", state);
		prcm_get_power_domain_state(DOM_NEON, &state);
		DPRINTK1("Current  NEON state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_CAM, &state);
		DPRINTK1("Previous  CAM state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_SGX, &state);
		DPRINTK1("Previous  SGX state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_USBHOST, &state);
		DPRINTK1("Previous  USBHOST state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_DSS, &state);
		DPRINTK1("Previous  DSS state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_PER, &state);
		DPRINTK1("Previous  PER state = %x\n", state);
		prcm_get_pre_power_domain_state(DOM_NEON, &state);
		DPRINTK1("Previous  NEON state = %x\n", state);
	}

	/* Turn on all power domains */
	ret1 = prcm_force_power_domain_state(DOM_IVA2, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_IVA2 failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_SGX, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_SGX failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_USBHOST, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_USBHOST failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_DSS, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_DSS failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_CAM, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_CAM failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_PER, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_PER failed\n");
		goto revert;
	}
	ret1 = prcm_force_power_domain_state(DOM_NEON, PRCM_ON);
	if (ret1 != PRCM_PASS) {
		DPRINTK1("prcm_force_power_domain_state DOM_NEON failed\n");
		goto revert;
	}
revert:
	/* Restore sleep/wakeup dependencies */
	CM_SLEEPDEP_SGX = cm_sleepdep_sgx;
	PM_WKDEP_SGX = pm_wkdep_sgx;
	CM_SLEEPDEP_USBHOST = cm_sleepdep_usb;
	PM_WKDEP_USBHOST = pm_wkdep_usb;
	CM_SLEEPDEP_DSS = cm_sleepdep_dss;
	CM_SLEEPDEP_CAM = cm_sleepdep_cam;
	CM_SLEEPDEP_PER = cm_sleepdep_per;
	PM_WKDEP_IVA2 = pm_wkdep_iva2;
	PM_WKDEP_MPU = pm_wkdep_mpu;
	PM_WKDEP_DSS = pm_wkdep_dss;
	PM_WKDEP_CAM = pm_wkdep_cam;
	PM_WKDEP_PER = pm_wkdep_per;
	PM_WKDEP_NEON = pm_wkdep_neon;

	/* Restore clock registers */
	CM_FCLKEN_IVA2 = ivaf;
	CM_FCLKEN1_CORE = core1f;
	CM_ICLKEN1_CORE = core1i;
	CM_ICLKEN2_CORE = core2i;
	CM_FCLKEN_SGX = sgxf;
	CM_ICLKEN_SGX = sgxi;
	CM_FCLKEN_USBHOST = usbf;
	CM_ICLKEN_USBHOST = usbi;
	CM_FCLKEN_WKUP = wkupf;
	CM_ICLKEN_WKUP = wkupi;
	CM_FCLKEN_DSS = dssf;
	CM_ICLKEN_DSS = dssi;
	CM_FCLKEN_CAM = camf;
	CM_ICLKEN_CAM = cami;
	CM_FCLKEN_PER = perf;
	CM_ICLKEN_PER = peri;

	if (ret || (ret1 != PRCM_PASS))
		return -1;

	return 0;
}
EXPORT_SYMBOL(powerapi_test);

int clkapi_test(void)
{
	u32 cm_clksel_core, cm_clksel_wkup, cm_clkout_ctrl;
	u32 cm_clksel_per, cm_clksel1_pll;
	u32 divider = 0, div, result;
	u32 proc_speed;
	u8 state;
	int ret = 0;
	u32 cm_clksel_sgx;

	/*baskup the clock registers*/
	cm_clksel_core = CM_CLKSEL_CORE;
	cm_clksel_wkup = CM_CLKSEL_WKUP;
	cm_clkout_ctrl = CM_CLKOUT_CTRL;
	cm_clksel_sgx = CM_CLKSEL_SGX;
	cm_clksel_per = CM_CLKSEL_PER;
	cm_clksel1_pll = CM_CLKSEL1_PLL;

	/*Test code for clock divisor setting and reading*/
	if (!prcm_clksel_set_divider(PRCM_48M_FCLK, 1))
		DPRINTK1("Divider for PRCM_48M_FCLK set to 1\n");
	if (!prcm_clksel_get_divider(PRCM_48M_FCLK, &divider))
		DPRINTK1("Divider for PRCM_48M_FCLK is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_12M_FCLK, 2))
		DPRINTK1("Divider for PRCM_12M_FCLK set to 2\n");
	if (!prcm_clksel_get_divider(PRCM_12M_FCLK, &divider))
		DPRINTK1("Divider for PRCM_12M_FCLK is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_SYS_CLKOUT2, 16))
		DPRINTK1("Divider for PRCM_SYS_CLKOUT2 set to 16\n");
	if (!prcm_clksel_get_divider(PRCM_SYS_CLKOUT2, &divider))
		DPRINTK1("Divider for PRCM_SYS_CLKOUT2 is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_L3_ICLK, 2))
		DPRINTK1("Divider for PRCM_L3_ICLK set to 2\n");
	if (!prcm_clksel_get_divider(PRCM_L3_ICLK, &divider))
		DPRINTK1("Divider for PRCM_L3_ICLK %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_L4_ICLK, 1))
		DPRINTK1("Divider for PRCM_L4_ICLK set to 1\n");
	if (!prcm_clksel_get_divider(PRCM_L4_ICLK, &divider))
		DPRINTK1("Divider for PRCM_L4_ICLK is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_RM_ICLK, 1))
		DPRINTK1("Divider for PRCM_RM_ICLK set to 1\n");
	if (!prcm_clksel_get_divider(PRCM_RM_ICLK, &divider))
		DPRINTK1("Divider for PRCM_RM_ICLK is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_SGX_FCLK, 3))
		DPRINTK1("Divider for PRCM_SGX_FCLK set to 3\n");
	if (!prcm_clksel_get_divider(PRCM_SGX_FCLK, &divider))
		DPRINTK1("Divider for PRCM_SGX_FCLK is %d\n", divider);
	if (!prcm_clksel_set_divider(PRCM_USIM, 10))
		DPRINTK1("Divider for PRCM_USIM set to 10\n");
	if (!prcm_clksel_get_divider(PRCM_USIM, &divider))
		DPRINTK1("Divider for PRCM_USIM is %d\n", divider);

	if (!prcm_clksel_set_divider(PRCM_SSI, 1))
		DPRINTK1("Divider for PRCM_SSI set to 1\n");
	if (!prcm_clksel_get_divider(PRCM_SSI, &divider))
		DPRINTK1("Divider for PRCM_SSI is %d\n", divider);
	/* Test code for clock source setting */
	ret = prcm_clk_set_source(PRCM_MCBSP1, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_MCBSP1 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_MCBSP2, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_MCBSP2 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_MCBSP3, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_MCBSP3 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_MCBSP4, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_MCBSP4 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_MCBSP5, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_MCBSP5 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_SYS_CLKOUT2, PRCM_SYS_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_SYS_CLKOUT2 set to PRCM_SYS"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT1, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT1 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT2, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT2 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT3, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT3 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT4, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT4 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT5, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT5 set to PRCM_SYS_32K"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT6, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT6 set to PRCM_SYS_32K_"
				"CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT7, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT7 set to PRCM_SYS_32K_"
				"CLK\n");
	ret = prcm_clk_set_source(PRCM_GPT8, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT8 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_GPT9, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT9 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_GPT10, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT10 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_GPT11, PRCM_SYS_32K_CLK);
	if (ret == PRCM_PASS)
		DPRINTK1("Source clock for PRCM_GPT11 set to PRCM_SYS_32K_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_USIM, PRCM_SYS_CLK);
	if (ret == PRCM_PASS)
		 DPRINTK1("Source clock for PRCM_USIM set to PRCM_SYS_CLK\n");
	ret = prcm_clk_set_source(PRCM_USIM, PRCM_DPLL4_M2X2_CLK);
	if (ret == PRCM_PASS)
		 DPRINTK1("Source clock for PRCM_USIM set to PRCM_DPLL4_M2X2"
				"_CLK\n");
	ret = prcm_clk_set_source(PRCM_USIM, PRCM_DPLL5_M2_CLK);
	if (ret == PRCM_PASS)
		 DPRINTK1("Source clock for PRCM_USIM set to PRCM_DPLL5_M2_CLK"
				"\n");
	ret = prcm_clk_set_source(PRCM_96M_CLK, PRCM_DPLL4_M2X2_CLK);
	if (ret == PRCM_PASS)
		 DPRINTK1("Source clock for PRCM_96M_CLK set to PRCM_DPLL4_"
				"M2X2_CLK\n");
	ret = prcm_clk_set_source(PRCM_96M_CLK, PRCM_SYS_CLK);
	if (ret == PRCM_PASS)
		 DPRINTK1("Source clock for PRCM_96M_CLK set to PRCM_SYS_CLK"
				"\n");
	if (ret != PRCM_PASS) {
		DPRINTK1("Some prcm_clk_set_source was not successful \n");
		goto revert;
	}

	if (!prcm_get_processor_speed(DOM_MPU, &proc_speed))
		DPRINTK1("MPU speed = %d\n", proc_speed);
	if (!prcm_get_processor_speed(DOM_IVA2, &proc_speed))
		DPRINTK1("IVA2 speed = %d\n", proc_speed);

	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 38000, &div))
		DPRINTK1("P-rate 38M,T-rate 38M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 19000, &div))
		DPRINTK1("P-rate 38M,T-rate 19M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 13000, &div))
		DPRINTK1("P-rate 38M,T-rate 9M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 9000, &div))
		DPRINTK1("P-rate 38M,T-rate 5M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 6000, &div))
		DPRINTK1("P-rate 38M,T-rate 3M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 2000, &div))
		DPRINTK1("P-rate 38M,T-rate 2M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_SSI, 38000, 39000, &div))
		DPRINTK1("P-rate 38M,T-rate 39M,DIV=%d\n", div);
	if (!prcm_clksel_round_rate(PRCM_DPLL3_M3X2_CLK, 96000, 24000, &div))
		DPRINTK1("P-rate 96M,T-rate 24M,DIV=%d\n", div);

	prcm_is_clock_domain_active(DOM_IVA2, &state);
	if (state)
		DPRINTK1("IVA2 domain is active\n");
	else
		DPRINTK1("IVA2 domain is inactive\n");

	prcm_get_devices_not_idle(DOM_CORE1, &result);
	DPRINTK1("Devices Not Idle Mask for CORE1 domain %x\n", result);

	prcm_get_initiators_not_standby(DOM_CORE1, &result);
	DPRINTK1("Devices Not Standby Mask for CORE1 domain %x\n", result);

	prcm_get_domain_functional_clocks(DOM_CORE1, &result);
	DPRINTK1("functional clock Mask for CORE1 domain %x\n", result);

	prcm_get_domain_interface_clocks(DOM_CORE1, &result);
	DPRINTK1("Interface clock Mask for CORE1 domain %x\n", result);

revert:
	/* Restore the clock registers */
	CM_CLKSEL_CORE = cm_clksel_core;
	CM_CLKSEL_WKUP = cm_clksel_wkup;
	CM_CLKOUT_CTRL = cm_clkout_ctrl;
	CM_CLKSEL_SGX = cm_clksel_sgx;
	CM_CLKSEL_PER = cm_clksel_per;
	CM_CLKSEL1_PLL = cm_clksel1_pll;

	if (ret != PRCM_PASS)
		return -1;

	return 0;
}
EXPORT_SYMBOL(clkapi_test);

int dpllapi_test(void)
{
	u32 dpll_rate;
	int ret = 0;

	/* Enable all DPLL's if not already done*/
	if (prcm_enable_dpll(DPLL1_MPU)) {
		DPRINTK1("DPLL1 enable failed\n");
		return -1;
	}
	if (prcm_enable_dpll(DPLL2_IVA2)) {
		DPRINTK1("DPLL2 enable failed\n");
		return -1;
	}
	/* Disable autoidle for DPLL5 during this test case is active */
	CM_AUTOIDLE2_PLL = 0x0;
	if (prcm_enable_dpll(DPLL5_PER2)) {
		DPRINTK1("DPLL5 enable failed\n");
		return -1;
	}
	/* Get all possible DPLL output rates */
	prcm_get_dpll_rate(PRCM_DPLL1_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL1_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL2_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL2_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2_CLK   = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M2X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M2X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL3_M3X2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL3_M3X2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DPLL5_M2_CLK, &dpll_rate);
	DPRINTK1("PRCM_DPLL5_M2_CLK = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_DSS, &dpll_rate);
	DPRINTK1("PRCM_DSS = %d\n", dpll_rate);
	prcm_get_dpll_rate(PRCM_CAM, &dpll_rate);
	DPRINTK1("PRCM_CAM = %d\n", dpll_rate);

	/* Put DPLL1/DPLL2 in BYPASS to change the configurations */
	if (prcm_put_dpll_in_bypass(DPLL1_MPU, LOW_POWER_BYPASS)
							!= PRCM_PASS) {
		DPRINTK1("Unable to put DPLL1 in Bypass\n");
		return -1;
	}
	if (prcm_put_dpll_in_bypass(DPLL2_IVA2, LOW_POWER_BYPASS)
							!= PRCM_PASS) {
		DPRINTK1("Unable to put DPLL2 in Bypass\n");
		goto revert0;
	}
	if (prcm_put_dpll_in_bypass(DPLL5_PER2, LOW_POWER_STOP)
							!= PRCM_PASS) {
		DPRINTK1("Unable to put DPLL5 in Bypass\n");