📄 prcm-regs.h
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/* * linux/arch/arm/mach-omap3/prcm-reg.h * * OMAP34XX Power Reset and Clock Management (PRCM) registers * * Copyright (C) 2007 Texas Instruments, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */#define __ARCH_ARM_MACH_OMAP3_PRCM_H#ifndef __ASSEMBLER__#define PRM_REG32(offset) __REG32(PRM_BASE + (offset))#define CM_REG32(offset) __REG32(CM_BASE + (offset))#define PRCM_REG32(offset) __REG32(PRM_BASE + (offset))#define SYSCONFIG_REG32(base, offset) __REG32(base + offset)#define DEFINE_REG(base, offset) __REG32(base + offset)#define CORE3_DPLL_MASK 0x7/* MASK values for core memory and logic resource */#define PRCM_CORE_MEM1ONBITS (0x3 << 16)#define PRCM_CORE_MEM2ONBITS (0x3 << 18)#define PRCM_CORE_MEMBIT1 (0x1 << 8)#define PRCM_CORE_MEMBIT2 (0x1 << 9)#define PRCM_CORE_MEMBIT (0x3 << 8)#define PRCM_CORE_PWRSTATEBIT1 0x1#define PRCM_CORE_PWRSTATEBIT2 0x2#define PRCM_CORE_LOGICBIT (0x1 << 2)#define PRCM_CORE_PWRSTATEOFF 0x0/* MASK values for some DPLL/CLOCK/POWER registers *//* DPLL1/2/3/5 enable/put_in_bypass MASK */#define DPLL_ENBIT_MASK 0xFFFFFFF8/* DPLL4 enable/put_in_bypass MASK */#define DPLL4_ENBIT_MASK 0xFFF8FFFF/* DPLL1/2/4 Divisor(N) value MASK */#define DPLL_N_MASK 0xFFFFFF80/* DPLL3 Divisor(N_ value MASK */#define DPLL3_N_MASK 0xFFFF80FF/* System clock divisor MASK */#define SYSCLK_DIV_MASK 0xFFFFFF3F/* External output clock 1/2 control MASK */#define EXTCLK_OUTCTRL_MASK 0xFFFFFF7F/* Power domain IN_TRANSITION MASK */#define PWSTST_INTRANS_MASK 0x00100000/* Power Domain state MASK */#define PWSTST_PWST_MASK 0x00000003/* Bit fields in RSTST registers */#define DOM_WKUP_RST 0x4#define COREDOM_WKUP_RST 0x8/* CM Module Registers *//* IVA2_CM Registers */#define CM_FCLKEN_IVA2 CM_REG32(0x0)#define CM_CLKEN_PLL_IVA2 CM_REG32(0x4)#define CM_IDLEST_IVA2 CM_REG32(0x20)#define CM_IDLEST_PLL_IVA2 CM_REG32(0x24)#define CM_AUTOIDLE_PLL_IVA2 CM_REG32(0x34)#define CM_CLKSEL1_PLL_IVA2 CM_REG32(0x40)#define CM_CLKSEL2_PLL_IVA2 CM_REG32(0x44)#define CM_CLKSTCTRL_IVA2 CM_REG32(0x48)#define CM_CLKSTST_IVA2 CM_REG32(0x4C)/* OCP System Register CM */#define CM_REVISION CM_REG32(0x800)#define CM_SYSCONFIG CM_REG32(0x810)/* MPU_CM Registers */#define CM_CLKEN_PLL_MPU CM_REG32(0x904)#define CM_IDLEST_MPU CM_REG32(0x920)#define CM_IDLEST_PLL_MPU CM_REG32(0x924)#define CM_AUTOIDLE_PLL_MPU CM_REG32(0x934)#define CM_CLKSEL1_PLL_MPU CM_REG32(0x940)#define CM_CLKSEL2_PLL_MPU CM_REG32(0x944)#define CM_CLKSTCTRL_MPU CM_REG32(0x948)#define CM_CLKSTST_MPU CM_REG32(0x94C)/* CORE_CM Registers */#define CM_FCLKEN1_CORE CM_REG32(0xA00)#define CM_ICLKEN1_CORE CM_REG32(0xA10)#define CM_ICLKEN2_CORE CM_REG32(0xA14)#define CM_IDLEST1_CORE CM_REG32(0xA20)#define CM_IDLEST2_CORE CM_REG32(0xA24)#define CM_AUTOIDLE1_CORE CM_REG32(0xA30)#define CM_AUTOIDLE2_CORE CM_REG32(0xA34)#define CM_CLKSEL_CORE CM_REG32(0xA40)#define CM_CLKSTCTRL_CORE CM_REG32(0xA48)#define CM_CLKSTST_CORE CM_REG32(0xA4C)#define CM_FCLKEN3_CORE CM_REG32(0xA08)#define CM_ICLKEN3_CORE CM_REG32(0xA18)#define CM_IDLEST3_CORE CM_REG32(0xA28)#define CM_AUTOIDLE3_CORE CM_REG32(0xA38)/* GFX_CM Registers */#define CM_FCLKEN_SGX CM_REG32(0xB00)#define CM_ICLKEN_SGX CM_REG32(0xB10)#define CM_IDLEST_SGX CM_REG32(0xB20)#define CM_CLKSEL_SGX CM_REG32(0xB40)#define CM_SLEEPDEP_SGX CM_REG32(0xB44)#define CM_CLKSTCTRL_SGX CM_REG32(0xB48)#define CM_CLKSTST_SGX CM_REG32(0xB4C)/* WKUP_CM Registers */#define CM_FCLKEN_WKUP CM_REG32(0xC00)#define CM_ICLKEN_WKUP CM_REG32(0xC10)#define CM_IDLEST_WKUP CM_REG32(0xC20)#define CM_AUTOIDLE_WKUP CM_REG32(0xC30)#define CM_CLKSEL_WKUP CM_REG32(0xC40)/* CM Clock control registers */#define CM_CLKEN_PLL CM_REG32(0xD00)#define CM_IDLEST_CKGEN CM_REG32(0xD20)#define CM_AUTOIDLE_PLL CM_REG32(0xD30)#define CM_CLKSEL1_PLL CM_REG32(0xD40)#define CM_CLKSEL2_PLL CM_REG32(0xD44)#define CM_CLKSEL3_PLL CM_REG32(0xD48)#define CM_CLKOUT_CTRL CM_REG32(0xD70)#define CM_CLKEN2_PLL CM_REG32(0xD04)#define CM_IDLEST2_CKGEN CM_REG32(0xD24)#define CM_AUTOIDLE2_PLL CM_REG32(0xD34)#define CM_CLKSEL4_PLL CM_REG32(0xD4C)#define CM_CLKSEL5_PLL CM_REG32(0xD50)/* DSS_CM Registers */#define CM_FCLKEN_DSS CM_REG32(0xE00)#define CM_ICLKEN_DSS CM_REG32(0xE10)#define CM_IDLEST_DSS CM_REG32(0xE20)#define CM_AUTOIDLE_DSS CM_REG32(0xE30)#define CM_CLKSEL_DSS CM_REG32(0xE40)#define CM_SLEEPDEP_DSS CM_REG32(0xE44)#define CM_CLKSTCTRL_DSS CM_REG32(0xE48)#define CM_CLKSTST_DSS CM_REG32(0xE4C)/* CAM_CM Registers */#define CM_FCLKEN_CAM CM_REG32(0xF00)#define CM_ICLKEN_CAM CM_REG32(0xF10)#define CM_IDLEST_CAM CM_REG32(0xF20)#define CM_AUTOIDLE_CAM CM_REG32(0xF30)#define CM_CLKSEL_CAM CM_REG32(0xF40)#define CM_SLEEPDEP_CAM CM_REG32(0xF44)#define CM_CLKSTCTRL_CAM CM_REG32(0xF48)#define CM_CLKSTST_CAM CM_REG32(0xF4C)/* PER_CM Registers */#define CM_FCLKEN_PER CM_REG32(0x1000)#define CM_ICLKEN_PER CM_REG32(0x1010)#define CM_IDLEST_PER CM_REG32(0x1020)#define CM_AUTOIDLE_PER CM_REG32(0x1030)#define CM_CLKSEL_PER CM_REG32(0x1040)#define CM_SLEEPDEP_PER CM_REG32(0x1044)#define CM_CLKSTCTRL_PER CM_REG32(0x1048)#define CM_CLKSTST_PER CM_REG32(0x104C)/* EMU_CM Registers */#define CM_CLKSEL1_EMU CM_REG32(0x1140)#define CM_CLKSTCTRL_EMU CM_REG32(0x1148)#define CM_CLKSTST_EMU CM_REG32(0x114C)#define CM_CLKSEL2_EMU CM_REG32(0x1150)#define CM_CLKSEL3_EMU CM_REG32(0x1154)/* Global Registers CM */#define CM_POLCTRL CM_REG32(0x129C)/* NEON_CM */#define CM_IDLEST_NEON CM_REG32(0x1320)#define CM_CLKSTCTRL_NEON CM_REG32(0x1348)/* USBHOST_CM registers */#define CM_FCLKEN_USBHOST CM_REG32(0x1400)#define CM_ICLKEN_USBHOST CM_REG32(0x1410)#define CM_IDLEST_USBHOST CM_REG32(0x1420)#define CM_AUTOIDLE_USBHOST CM_REG32(0x1430)#define CM_SLEEPDEP_USBHOST CM_REG32(0x1444)#define CM_CLKSTCTRL_USBHOST CM_REG32(0x1448)#define CM_CLKSTST_USBHOST CM_REG32(0x144C)/* PRM Module Registers *//* IVA2_PRM */#define RM_RSTCTRL_IVA2 PRM_REG32(0x50)#define RM_RSTST_IVA2 PRM_REG32(0x58)#define PM_WKDEP_IVA2 PRM_REG32(0xC8)#define PM_PWSTCTRL_IVA2 PRM_REG32(0xE0)#define PM_PWSTST_IVA2 PRM_REG32(0xE4)#define PM_PREPWSTST_IVA2 PRM_REG32(0xE8)#define PRM_IRQSTATUS_IVA2 PRM_REG32(0xF8)#define PRM_IRQENABLE_IVA2 PRM_REG32(0xFC)/* OCP System Registers PRM */#define PRM_REVISION PRM_REG32(0x804)#define PRM_SYSCONFIG PRM_REG32(0x814)#define PRM_IRQSTATUS_MPU PRM_REG32(0x818)#define PRM_IRQENABLE_MPU PRM_REG32(0x81C)/* MPU_PRM Registers */#define RM_RSTST_MPU PRM_REG32(0x958)#define PM_WKDEP_MPU PRM_REG32(0x9C8)#define PM_EVGENCTRL_MPU PRM_REG32(0x9D4)#define PM_EVGENONTIM_MPU PRM_REG32(0x9D8)#define PM_EVGENOFFTIM_MPU PRM_REG32(0x9DC)#define PM_PWSTCTRL_MPU PRM_REG32(0x9E0)#define PM_PWSTST_MPU PRM_REG32(0x9E4)#define PM_PREPWSTST_MPU PRM_REG32(0x9E8)/* CORE_PRM Registers */#define RM_RSTCTRL_CORE PRM_REG32(0xA50)#define RM_RSTST_CORE PRM_REG32(0xA58)#define PM_WKEN1_CORE PRM_REG32(0xAA0)#define PM_MPUGRPSEL1_CORE PRM_REG32(0xAA4)#define PM_IVA2GRPSEL1_CORE PRM_REG32(0xAA8)#define PM_WKST1_CORE PRM_REG32(0xAB0)#define PM_PWSTCTRL_CORE PRM_REG32(0xAE0)#define PM_PWSTST_CORE PRM_REG32(0xAE4)#define PM_PREPWSTST_CORE PRM_REG32(0xAE8)#define PM_WKST3_CORE PRM_REG32(0xAB8)#define PM_WKEN3_CORE PRM_REG32(0xAF0)#define PM_IVA2GRPSEL3_CORE PRM_REG32(0xAF4)#define PM_MPUGRPSEL3_CORE PRM_REG32(0xAF8)/* GFX_PRM Registers */#define RM_RSTST_SGX PRM_REG32(0xB58)#define PM_WKDEP_SGX PRM_REG32(0xBC8)#define PM_PWSTCTRL_SGX PRM_REG32(0xBE0)#define PM_PWSTST_SGX PRM_REG32(0xBE4)#define PM_PREPWSTST_SGX PRM_REG32(0xBE8)/* WKUP_PRM Registers */#define PM_WKEN_WKUP PRM_REG32(0xCA0)#define PM_MPUGRPSEL_WKUP PRM_REG32(0xCA4)#define PM_IVA2GRPSEL_WKUP PRM_REG32(0xCA8)#define PM_WKST_WKUP PRM_REG32(0xCB0)/* Clock control registers PRM */⌨️ 快捷键说明
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