clock_34xx.h

omap3 linux 2.6 用nocc去除了冗余代码

/*
 * linux/arch/arm/mach-omap3/clock.h
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <[e-mail]>
 *
 * Based on OMAP2 clock framework created by
 * Richard Woodruff <[e-mail]>
 *
 * Copyright (C) 2004 Nokia corporation
 * Written by Tuukka Tikkanen <[e-mail]>
 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 *
 */

#define __ARCH_ARM_MACH_OMAP3_CLOCK_H

#include <asm/arch/prcm.h>

/* Macro to enable clock control via clock framework */
#define ENABLE_CLOCKCONTROL 1

static void omap3_clk_recalc(struct clk *clk);
static void omap3_followparent_recalc(struct clk *clk);
static void omap3_propagate_rate(struct clk *clk);
static void omap3_table_recalc(struct clk *clk);
static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate);
static int omap3_select_table_rate(struct clk *clk, unsigned long rate);


/*-------------------------------------------------------------------------
 * 34xx clock tree.
 *
 * NOTE:
 *	In many cases here we are assigning a 'default' parent. In many
 *	cases the parent is selectable. The get/set parent calls will also
 *  	switch sources.
 *
 *	Several sources are given initial rates which may be wrong, this will
 *	be fixed up in the init func.
 *
 *	Things are broadly separated below by clock domains. It is
 *	noteworthy that most periferals have dependencies on multiple clock
 *	domains. Many get their interface clocks from the L4 domain, but get
 *	functional clocks from fixed sources or other core domain derived
 *	clocks.
 *-------------------------------------------------------------------------
 */
/* initial hardcode defines */
#define S_OSC	19200000
#define S_32K	32768
#define S_ALT	54000000

#define S12M	12000000
#define S13M	13000000
#define S19M	19200000
#define S26M	26000000
#define S38M	38400000

#define S625M	625000000
#define S550M	550000000
#define S500M	500000000
#define S250M	250000000
#define S125M	125000000
#define	S19M	19200000
#define S120M	120000000

#define S96M	96000000
#define S166M	166000000
#define S83M	83000000

#define RATE_IN_343X    (1 << 0)

struct vdd_prcm_config {
	unsigned long speed;
	unsigned long opp;
	unsigned char flags;
};


static struct vdd_prcm_config vdd1_rate_table[] = {
			{0, 0, 0},
	/*OPP1*/	{S125M, PRCM_VDD1_OPP1, RATE_IN_343X},
	/*OPP2*/	{S250M, PRCM_VDD1_OPP2, RATE_IN_343X},
	/*OPP3*/	{S500M, PRCM_VDD1_OPP3, RATE_IN_343X},
	/*OPP4*/	{S550M, PRCM_VDD1_OPP4, RATE_IN_343X},
	/*OPP5*/	{S625M, PRCM_VDD1_OPP5, RATE_IN_343X},
};

static struct vdd_prcm_config vdd2_rate_table[] = {
			{0, 0, 0},
	/*OPP1*/	{S19M, PRCM_VDD2_OPP1, RATE_IN_343X},
	/*OPP2*/	{S83M, PRCM_VDD2_OPP2, RATE_IN_343X},
	/*OPP3*/	{S166M, PRCM_VDD2_OPP3, RATE_IN_343X},
};
#define MAX_VDD1_OPP 5
#define MAX_VDD2_OPP 3

/*
 * Base External input clocks
 */

/* 32K clock */
static struct clk sys_32k_ck = {
	.name	= "sys_32k_ck",
	.prcmid	= PRCM_SYS_32K_CLK,
	.rate   = S_32K,
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_FIXED |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES,
	.recalc	= &omap3_propagate_rate,
};

static struct clk osc_ck = {	/* (*12, *13, 19.2, *26, 38.4)MHz */
	.name	= "osc_ck",
	.rate   = S_OSC,		/* fixed up in clock init */
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_FIXED |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES,
	.recalc	= &omap3_propagate_rate,
};

static struct clk sys_ck = {	/* (*12, *13, 19.2, 26, 38.4)MHz */
	.name	= "sys_ck",	/* ~ ref_clk also */
	.parent	= &osc_ck,
	.rate   = S_OSC,
	.prcmid	= PRCM_SYS_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_FIXED |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES,
	.recalc	= &omap3_clk_recalc,
};

static struct clk sys_alt_ck = {
	.name	= "sys_alt_ck",
	.rate   = S_ALT,
	.prcmid	= PRCM_SYS_ALT_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_FIXED |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES,
	.recalc	= &omap3_propagate_rate,
};

static struct clk usim_fck = {
	.name	= "usim_fck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_USIM,
	.flags	= CLOCK_IN_OMAP343X | F_CLK | RATE_CKCTL | SRC_SEL,
	.recalc	= &omap3_clk_recalc,
};

static struct clk usim_ick = {
	.name	= "usim_ick",
	.parent	= &sys_ck,
	.prcmid	= PRCM_USIM,
	.flags	= CLOCK_IN_OMAP343X | I_CLK,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk usbhost2_fck = {
	.name	= "usbhost2_fck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_USBHOST2,
	.flags	= CLOCK_IN_OMAP343X | F_CLK | DPLL_OUTPUT | POWER_ON_REQUIRED,
	.recalc	= &omap3_clk_recalc,
};

static struct clk core_ck = {	/* Same as DPLL3_M2_CLK */
	.name	= "core_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL3_M2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT |
		  VDD2_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk core_x2_ck = {	/* Same as DPLL3_M2X2_CLK */
	.name	= "core_x2_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL3_M2X2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT |
		  VDD2_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk cpefuse_fck = {
	.name	= "cpefuse_fck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_CPEFUSE,
	.flags	= CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk ts_fck = {
	.name	= "ts_fck",
	.parent	= &sys_32k_ck,
	.prcmid	= PRCM_TS,
	.flags	= CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk emul_core_alwon_ck = {	/* Same as DPLL3_M3X2_CLK */
	.name	= "emul_core_alwon_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL3_M3X2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk cm_96m_ck = {	/* same as DPLL4_M2X2_CLK */
	.name	= "cm_96m_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL4_M2X2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT,
	.recalc	= &omap3_clk_recalc,

};

static struct clk func_96m_ck = {
	.name	= "func_96m_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_96M_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  SRC_SEL,
	.recalc	= &omap3_followparent_recalc,

};

static struct clk dpll4_m3x2_ck = {
	.name	= "dpll4_m3x2_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL4_M3X2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk emul_per_alwon_ck = {	/* same as DPLL4_M6X2_CLK */
	.name	= "emul_per_alwon_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_DPLL4_M6X2_CLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  DPLL_OUTPUT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk func_48m_ck = {
	.name	= "func_48m_ck",
	.parent	= &func_96m_ck,	/*can be sys_alt_ck too */
	.prcmid	= PRCM_48M_FCLK,
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_PROPAGATES |
		  ALWAYS_ENABLED |
		  RATE_CKCTL |
		  SRC_SEL,
	.recalc	= &omap3_clk_recalc,
};

static struct clk func_12m_ck = {
	.name	= "func_12m_ck",
	.parent	= &func_48m_ck,
	.prcmid	= PRCM_12M_FCLK,
	.flags	= CLOCK_IN_OMAP343X |
		  RATE_PROPAGATES |
		  ALWAYS_ENABLED |
		  RATE_CKCTL,
	.recalc	= &omap3_clk_recalc,
};

static struct clk dss_tv_fck = {
	/* This node controls dss_96m_fck too */
	.name	= "dss_tv_fck",
	.parent	= &dpll4_m3x2_ck,	/*can be sys_alt_ck too */
	.prcmid	= PRCM_TVOUT,
	.flags	= CLOCK_IN_OMAP343X |
		  SRC_SEL |
		  F_CLK |
		  POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

/* External output clocks */
static struct clk sys_clkout1 = {
/*May need to revisit this - sys_clkout1 can be output clock too */
	.name	= "sys_clkout1",
	.parent	= &osc_ck,
	.prcmid	= PRCM_SYS_CLKOUT1,
	.flags	= CLOCK_IN_OMAP343X,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk sys_clkout2 = {
	.name	= "sys_clkout2",
	.parent	= &sys_ck,
/* Can be core_ck,dss_tv_fck or func_96m_ck too */
	.prcmid	= PRCM_SYS_CLKOUT2,
	.flags	= CLOCK_IN_OMAP343X | RATE_CKCTL | SRC_SEL,
	.recalc	= &omap3_clk_recalc,
};

static struct clk l3_ck = {
	.name	= "l3_ck",
	.parent	= &core_ck,
	.prcmid	= PRCM_L3_ICLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  RATE_CKCTL |
		  VDD2_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk l4_ck = {
	.name	= "l4_ck",
	.parent	= &l3_ck,
	.prcmid	= PRCM_L4_ICLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  RATE_CKCTL |
		  VDD2_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk rm_ck = {
	.name	= "rm_ck",
	.parent	= &l4_ck,
	.prcmid	= PRCM_RM_ICLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  RATE_CKCTL |
		  VDD2_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

static struct clk dpll1_fck = {
	.name	= "dpll1_fck",
	.parent	= &core_ck,
	.prcmid	= PRCM_DPLL1_FCLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  RATE_CKCTL,
	.recalc	= &omap3_clk_recalc,
};

static struct clk dpll2_fck = {
	.name	= "dpll2_fck",
	.parent	= &core_ck,
	.prcmid	= PRCM_DPLL2_FCLK,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  RATE_CKCTL,
	.recalc	= &omap3_clk_recalc,
};

/* Clocks in MPU Power Domain */
static struct clk mpu_ck = {	/* Control cpu */
	.name	= "mpu_ck",
	.parent	= &sys_ck,
	.prcmid	= DOM_MPU,
	.flags	= CLOCK_IN_OMAP343X |
		  ALWAYS_ENABLED |
		  RATE_PROPAGATES |
		  VDD1_CONFIG_PARTICIPANT,
	.recalc	= &omap3_clk_recalc,
};

/* Clocks in IVA2 Power Domain */
static struct clk iva2_ck = {
	.name	= "iva2_ck",
	.parent	= &sys_ck,
	.prcmid	= PRCM_IVA2,
	.flags	= CLOCK_IN_OMAP343X |
		  F_CLK |
		  RATE_PROPAGATES |
		  VDD1_CONFIG_PARTICIPANT |
		  POWER_ON_REQUIRED,
	.recalc	= &omap3_clk_recalc,
};

/* GFX domain clocks */
/* In the GFX domain, GFX_L3_FCLK and GFX_L3_ICLK are derived
 from l3_iclk and have one gating control bit (CM_ICLKEN_GFX.EN_GFX).
 So another clock (gfx_l3_ck) is represented in the clock tree with
 two child clocks - gfx_fclk and gfx_iclk
 When either of these child clocks are enabled, the EN_GFX bit will
 be set to 1, making sure that the clock is supplied */

static struct clk sgx_fck = {
	.name	= "sgx_fck",
	.parent	= &core_ck,
	.flags = CLOCK_IN_OMAP343X | SRC_SEL | F_CLK | RATE_CKCTL |
		  POWER_ON_REQUIRED,
	.prcmid	= PRCM_SGX_FCLK,
	.recalc	= &omap3_clk_recalc,
};

static struct clk sgx_ick = {
	.name	= "sgx_ick",
	.parent	= &l3_ck,
	.flags	= CLOCK_IN_OMAP343X | I_CLK,
	.prcmid	= PRCM_SGX_ICLK,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk hsusb_ick = {
	.name	= "hsusb_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_HSOTG,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk usbhost_ick = {
	.name	= "usbhost_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_USBHOST1,
	.flags	= CLOCK_IN_OMAP343X | I_CLK,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk usbhost1_fck = {
	.name	= "usbhost1_fck",
	.parent	= &func_48m_ck,
	.prcmid	= PRCM_USBHOST1,
	.flags	= CLOCK_IN_OMAP343X | F_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk sdrc_ick = {
	.name	= "sdrc_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_SDRC,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | ALWAYS_ENABLED | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk pka_ick = {
	.name	= "pka_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_PKA,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk aes2_ick = {
	.name	= "aes2_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_AES2,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk sha12_ick = {
	.name	= "sha12_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_SHA12,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk des2_ick = {
	.name	= "des2_ick",
	.parent	= &l3_ck,
	.prcmid	= PRCM_DES2,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk aes1_ick = {
	.name	= "aes1_ick",
	.parent	= &l4_ck,
	.prcmid	= PRCM_AES1,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,
};

static struct clk sha11_ick = {
	.name	= "sha11_ick",
	.parent	= &l4_ck,
	.prcmid	= PRCM_SHA11,
	.flags	= CLOCK_IN_OMAP343X | I_CLK | POWER_ON_REQUIRED,
	.recalc	= &omap3_followparent_recalc,