display.c

来自「omap3 linux 2.6 用nocc去除了冗余代码」· C语言 代码 · 共 2,061 行 · 第 1/5 页

			DISPC_CONTROL_GOLCD);
	}
}

/*
 * Save the DSS state before doing a GO LCD/DIGITAL
 */

void
omap2_disp_save_ctx(int ltype)
{
	int v1=0, v2=1;
	struct omap24xx_dispc_regs *dispc = &dss_ctx.dispc;

	switch(ltype){
	case OMAP_DSS_GENERIC:
		dss_ctx.sysconfig = dss_reg_in(DSS_SYSCONFIG);
		dss_ctx.control = dss_reg_in(DSS_CONTROL);
		dss_ctx.sdi_control = dss_reg_in(DSS_SDI_CONTROL);
		dss_ctx.pll_control = dss_reg_in(DSS_PLL_CONTROL);
		break;

	case OMAP_DSS_DISPC_GENERIC:
		dispc->revision  = dispc_reg_in(DISPC_REVISION);
		dispc->sysconfig = dispc_reg_in(DISPC_SYSCONFIG);
		dispc->sysstatus = dispc_reg_in(DISPC_SYSSTATUS);
		dispc->irqstatus = dispc_reg_in(DISPC_IRQSTATUS);
		dispc->irqenable = dispc_reg_in(DISPC_IRQENABLE);
		dispc->control   = dispc_reg_in(DISPC_CONTROL);
		dispc->config    = dispc_reg_in(DISPC_CONFIG);
		dispc->capable   = dispc_reg_in(DISPC_CAPABLE);
		dispc->default_color0 = dispc_reg_in(DISPC_DEFAULT_COLOR0);
		dispc->default_color1 = dispc_reg_in(DISPC_DEFAULT_COLOR1);
		dispc->trans_color0   = dispc_reg_in(DISPC_TRANS_COLOR0);
		dispc->trans_color1   = dispc_reg_in(DISPC_TRANS_COLOR1);
		dispc->line_status    = dispc_reg_in(DISPC_LINE_STATUS);
		dispc->line_number    = dispc_reg_in(DISPC_LINE_NUMBER);
		dispc->data_cycle1    = dispc_reg_in(DISPC_DATA_CYCLE1);
		dispc->data_cycle2    = dispc_reg_in(DISPC_DATA_CYCLE2);
		dispc->data_cycle3    = dispc_reg_in(DISPC_DATA_CYCLE3);
		dispc->timing_h = dispc_reg_in(DISPC_TIMING_H);
		dispc->timing_v = dispc_reg_in(DISPC_TIMING_V);
		dispc->pol_freq = dispc_reg_in(DISPC_POL_FREQ);
		dispc->divisor  = dispc_reg_in(DISPC_DIVISOR);
		dispc->global_alpha = dispc_reg_in(DISPC_GLOBAL_ALPHA);
		dispc->size_lcd = dispc_reg_in(DISPC_SIZE_LCD);
		dispc->size_dig = dispc_reg_in(DISPC_SIZE_DIG);

	case OMAP2_GRAPHICS:
		dispc->gfx_ba0  = dispc_reg_in(DISPC_GFX_BA0);
		dispc->gfx_ba1  = dispc_reg_in(DISPC_GFX_BA1);
		dispc->gfx_position   = dispc_reg_in(DISPC_GFX_POSITION);
		dispc->gfx_size       = dispc_reg_in(DISPC_GFX_SIZE);
		dispc->gfx_attributes = dispc_reg_in(DISPC_GFX_ATTRIBUTES);
		dispc->gfx_fifo_size  = dispc_reg_in(DISPC_GFX_FIFO_SIZE);
		dispc->gfx_fifo_threshold = dispc_reg_in(DISPC_GFX_FIFO_THRESHOLD);
		dispc->gfx_row_inc        = dispc_reg_in(DISPC_GFX_ROW_INC);
		dispc->gfx_pixel_inc      = dispc_reg_in(DISPC_GFX_PIXEL_INC);
		dispc->gfx_window_skip    = dispc_reg_in(DISPC_GFX_WINDOW_SKIP);
		dispc->gfx_table_ba       = dispc_reg_in(DISPC_GFX_TABLE_BA);
	break;

	case OMAP2_VIDEO1:
		dispc->vid1_ba0 = dispc_reg_in(DISPC_VID_BA0(v1));
		dispc->vid1_ba1 = dispc_reg_in(DISPC_VID_BA0(v1));
		dispc->vid1_position = dispc_reg_in(DISPC_VID_POSITION(v1));
		dispc->vid1_size = dispc_reg_in(DISPC_VID_SIZE(v1));
		dispc->vid1_attributes = dispc_reg_in(DISPC_VID_ATTRIBUTES(v1));
		dispc->vid1_fifo_size  = dispc_reg_in(DISPC_VID_FIFO_SIZE(v1));
		dispc->vid1_fifo_threshold = dispc_reg_in(DISPC_VID_FIFO_THRESHOLD(v1));
		dispc->vid1_row_inc   = dispc_reg_in(DISPC_VID_ROW_INC(v1));
		dispc->vid1_pixel_inc = dispc_reg_in(DISPC_VID_PIXEL_INC(v1));
		dispc->vid1_fir 	     = dispc_reg_in(DISPC_VID_FIR(v1));
		dispc->vid1_accu0 = dispc_reg_in(DISPC_VID_ACCU0(v1));
		dispc->vid1_accu1 = dispc_reg_in(DISPC_VID_ACCU1(v1));
		dispc->vid1_picture_size = dispc_reg_in(DISPC_VID_PICTURE_SIZE(v1));
		dispc->vid1_fir_coef_h0  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,0));
		dispc->vid1_fir_coef_h1  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,1));
		dispc->vid1_fir_coef_h2  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,2));
		dispc->vid1_fir_coef_h3  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,3));
		dispc->vid1_fir_coef_h4  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,4));
		dispc->vid1_fir_coef_h5  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,5));
		dispc->vid1_fir_coef_h6  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,6));
		dispc->vid1_fir_coef_h7  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,7));
		dispc->vid1_fir_coef_hv0 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,0));
		dispc->vid1_fir_coef_hv1 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,1));
		dispc->vid1_fir_coef_hv2 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,2));
		dispc->vid1_fir_coef_hv3 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,3));
		dispc->vid1_fir_coef_hv4 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,4));
		dispc->vid1_fir_coef_hv5 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,5));
		dispc->vid1_fir_coef_hv6 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,6));
		dispc->vid1_fir_coef_hv7 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,7));
		dispc->vid1_conv_coef0   = dispc_reg_in(DISPC_VID_CONV_COEF0(v1));
		dispc->vid1_conv_coef1   = dispc_reg_in(DISPC_VID_CONV_COEF1(v1));
		dispc->vid1_conv_coef2   = dispc_reg_in(DISPC_VID_CONV_COEF2(v1));
		dispc->vid1_conv_coef3   = dispc_reg_in(DISPC_VID_CONV_COEF3(v1));
		dispc->vid1_conv_coef4   = dispc_reg_in(DISPC_VID_CONV_COEF4(v1));
	break;

	case OMAP2_VIDEO2:
		dispc->vid2_ba0 = dispc_reg_in(DISPC_VID_BA0(v2));
		dispc->vid2_ba1 = dispc_reg_in(DISPC_VID_BA1(v2));
		dispc->vid2_position = dispc_reg_in(DISPC_VID_POSITION(v2));
		dispc->vid2_size = dispc_reg_in(DISPC_VID_SIZE(v2));
		dispc->vid2_attributes = dispc_reg_in(DISPC_VID_ATTRIBUTES(v2));
		dispc->vid2_fifo_size  = dispc_reg_in(DISPC_VID_FIFO_SIZE(v2));
		dispc->vid2_fifo_threshold = dispc_reg_in(DISPC_VID_FIFO_THRESHOLD(v2));
		dispc->vid2_row_inc   = dispc_reg_in(DISPC_VID_ROW_INC(v2));
		dispc->vid2_pixel_inc = dispc_reg_in(DISPC_VID_PIXEL_INC(v2));
		dispc->vid2_fir = dispc_reg_in(DISPC_VID_FIR(v2));
		dispc->vid2_accu0 = dispc_reg_in(DISPC_VID_ACCU0(v2));
		dispc->vid2_accu1 = dispc_reg_in(DISPC_VID_ACCU1(v2));
		dispc->vid2_picture_size = dispc_reg_in(DISPC_VID_PICTURE_SIZE(v2));
		dispc->vid2_fir_coef_h0  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,0));
		dispc->vid2_fir_coef_h1  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,1));
		dispc->vid2_fir_coef_h2  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,2));
		dispc->vid2_fir_coef_h3  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,3));
		dispc->vid2_fir_coef_h4  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,4));
		dispc->vid2_fir_coef_h5  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,5));
		dispc->vid2_fir_coef_h6  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,6));
		dispc->vid2_fir_coef_h7  = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,7));
		dispc->vid2_fir_coef_hv0 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,0));
		dispc->vid2_fir_coef_hv1 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,1));
		dispc->vid2_fir_coef_hv2 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,2));
		dispc->vid2_fir_coef_hv3 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,3));
		dispc->vid2_fir_coef_hv4 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,4));
		dispc->vid2_fir_coef_hv5 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,5));
		dispc->vid2_fir_coef_hv6 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,6));
		dispc->vid2_fir_coef_hv7 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,7));
		dispc->vid2_conv_coef0   = dispc_reg_in(DISPC_VID_CONV_COEF0(v2));
		dispc->vid2_conv_coef1   = dispc_reg_in(DISPC_VID_CONV_COEF1(v2));
		dispc->vid2_conv_coef2   = dispc_reg_in(DISPC_VID_CONV_COEF2(v2));
		dispc->vid2_conv_coef3   = dispc_reg_in(DISPC_VID_CONV_COEF3(v2));
		dispc->vid2_conv_coef4   = dispc_reg_in(DISPC_VID_CONV_COEF4(v2));
	break;
	}
	layer[ltype].ctx_valid = 1;
}

void omap2_disp_save_initstate(int ltype)
{
	unsigned long flags;

	spin_lock_irqsave(&dss_lock, flags);
	omap2_disp_save_ctx(ltype);
	spin_unlock_irqrestore(&dss_lock, flags);
}

/* 
 *  NOte, that VENC registers are not restored here 
 *  Note, that DISPC_CONTROL register is not restored here
 */
void
omap2_disp_restore_ctx(int ltype)
{
	int v1=0, v2=1;
	struct omap24xx_dispc_regs *dispc = &dss_ctx.dispc;

	if (layer[ltype].ctx_valid == 0)
		return;

	switch(ltype){
	case OMAP_DSS_GENERIC:
		dss_reg_out(DSS_SYSCONFIG, dss_ctx.sysconfig);
		dss_reg_out(DSS_CONTROL, dss_ctx.control);
		dss_reg_out(DSS_SDI_CONTROL, dss_ctx.sdi_control);
		dss_reg_out(DSS_PLL_CONTROL, dss_ctx.pll_control);
		break;

	case OMAP_DSS_DISPC_GENERIC:
		dispc_reg_out(DISPC_SYSCONFIG, dispc->sysconfig);
		dispc_reg_out(DISPC_IRQENABLE, dispc->irqenable);
		dispc_reg_out(DISPC_CONFIG, dispc->config);
		dispc_reg_out(DISPC_DEFAULT_COLOR0, dispc->default_color0);
		dispc_reg_out(DISPC_DEFAULT_COLOR1, dispc->default_color1);
		dispc_reg_out(DISPC_TRANS_COLOR0, dispc->trans_color0);
		dispc_reg_out(DISPC_TRANS_COLOR1, dispc->trans_color1);
		dispc_reg_out(DISPC_LINE_NUMBER, dispc->line_number);
		dispc_reg_out(DISPC_DATA_CYCLE1, dispc->data_cycle1);
		dispc_reg_out(DISPC_DATA_CYCLE2, dispc->data_cycle2);
		dispc_reg_out(DISPC_DATA_CYCLE3, dispc->data_cycle3);
		dispc_reg_out(DISPC_TIMING_H, dispc->timing_h);
		dispc_reg_out(DISPC_TIMING_V, dispc->timing_v);
		dispc_reg_out(DISPC_POL_FREQ, dispc->pol_freq);
		dispc_reg_out(DISPC_DIVISOR, dispc->divisor);
		dispc_reg_out(DISPC_GLOBAL_ALPHA,dispc->global_alpha);
		dispc_reg_out(DISPC_SIZE_LCD, dispc->size_lcd);
		dispc_reg_out(DISPC_SIZE_DIG, dispc->size_dig);
		break;

	case OMAP2_GRAPHICS:
		dispc_reg_out(DISPC_GFX_BA0, dispc->gfx_ba0);
		dispc_reg_out(DISPC_GFX_BA1, dispc->gfx_ba1);
		dispc_reg_out(DISPC_GFX_POSITION, dispc->gfx_position);
		dispc_reg_out(DISPC_GFX_SIZE, dispc->gfx_size);
		dispc_reg_out(DISPC_GFX_ATTRIBUTES, dispc->gfx_attributes);
		dispc_reg_out(DISPC_GFX_FIFO_SIZE,dispc->gfx_fifo_size);
		dispc_reg_out(DISPC_GFX_FIFO_THRESHOLD, dispc->gfx_fifo_threshold);
		dispc_reg_out(DISPC_GFX_ROW_INC, dispc->gfx_row_inc);
		dispc_reg_out(DISPC_GFX_PIXEL_INC, dispc->gfx_pixel_inc);
		dispc_reg_out(DISPC_GFX_WINDOW_SKIP, dispc->gfx_window_skip);
		dispc_reg_out(DISPC_GFX_TABLE_BA, dispc->gfx_table_ba);

	break;

	case OMAP2_VIDEO1:
		dispc_reg_out(DISPC_VID_BA0(v1), dispc->vid1_ba0);
		dispc_reg_out(DISPC_VID_BA1(v1), dispc->vid1_ba1);
		dispc_reg_out(DISPC_VID_POSITION(v1), dispc->vid1_position);
		dispc_reg_out(DISPC_VID_SIZE(v1), dispc->vid1_size);
		dispc_reg_out(DISPC_VID_ATTRIBUTES(v1), dispc->vid1_attributes);
		dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v1),dispc->vid1_fifo_threshold);
		dispc_reg_out(DISPC_VID_ROW_INC(v1), dispc->vid1_row_inc);
		dispc_reg_out(DISPC_VID_PIXEL_INC(v1), dispc->vid1_pixel_inc);
		dispc_reg_out(DISPC_VID_FIR(v1), dispc->vid1_fir);
		dispc_reg_out(DISPC_VID_ACCU0(v1), dispc->vid1_accu0);
		dispc_reg_out(DISPC_VID_ACCU1(v1), dispc->vid1_accu1);
		dispc_reg_out(DISPC_VID_PICTURE_SIZE(v1), dispc->vid1_picture_size);

		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,0), dispc->vid1_fir_coef_h0);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,1), dispc->vid1_fir_coef_h1);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,2), dispc->vid1_fir_coef_h2);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,3), dispc->vid1_fir_coef_h3);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,4), dispc->vid1_fir_coef_h4);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,5), dispc->vid1_fir_coef_h5);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,6), dispc->vid1_fir_coef_h6);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,7), dispc->vid1_fir_coef_h7);

		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,0), dispc->vid1_fir_coef_hv0);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,1), dispc->vid1_fir_coef_hv1);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,2), dispc->vid1_fir_coef_hv2);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,3), dispc->vid1_fir_coef_hv3);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,4), dispc->vid1_fir_coef_hv4);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,5), dispc->vid1_fir_coef_hv5);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,6), dispc->vid1_fir_coef_hv6);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,7), dispc->vid1_fir_coef_hv7);

		dispc_reg_out(DISPC_VID_CONV_COEF0(v1), dispc->vid1_conv_coef0);
		dispc_reg_out(DISPC_VID_CONV_COEF1(v1), dispc->vid1_conv_coef1);
		dispc_reg_out(DISPC_VID_CONV_COEF2(v1), dispc->vid1_conv_coef2);
		dispc_reg_out(DISPC_VID_CONV_COEF3(v1), dispc->vid1_conv_coef3);
		dispc_reg_out(DISPC_VID_CONV_COEF4(v1), dispc->vid1_conv_coef4);
	break;

	case OMAP2_VIDEO2:
		dispc_reg_out(DISPC_VID_BA0(v2), dispc->vid2_ba0);
		dispc_reg_out(DISPC_VID_BA1(v2), dispc->vid2_ba1);
		dispc_reg_out(DISPC_VID_POSITION(v2), dispc->vid2_position);
		dispc_reg_out(DISPC_VID_SIZE(v2), dispc->vid2_size);
		dispc_reg_out(DISPC_VID_ATTRIBUTES(v2), dispc->vid2_attributes);
		dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v2),dispc->vid2_fifo_threshold);
		dispc_reg_out(DISPC_VID_ROW_INC(v2), dispc->vid2_row_inc);
		dispc_reg_out(DISPC_VID_PIXEL_INC(v2), dispc->vid2_pixel_inc);
		dispc_reg_out(DISPC_VID_FIR(v2), dispc->vid2_fir);
		dispc_reg_out(DISPC_VID_ACCU0(v2), dispc->vid2_accu0);
		dispc_reg_out(DISPC_VID_ACCU1(v2), dispc->vid2_accu1);
		dispc_reg_out(DISPC_VID_PICTURE_SIZE(v2), dispc->vid2_picture_size);

		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,0), dispc->vid2_fir_coef_h0);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,1), dispc->vid2_fir_coef_h1);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,2), dispc->vid2_fir_coef_h2);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,3), dispc->vid2_fir_coef_h3);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,4), dispc->vid2_fir_coef_h4);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,5), dispc->vid2_fir_coef_h5);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,6), dispc->vid2_fir_coef_h6);
		dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,7), dispc->vid2_fir_coef_h7);

		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,0), dispc->vid2_fir_coef_hv0);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,1), dispc->vid2_fir_coef_hv1);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,2), dispc->vid2_fir_coef_hv2);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,3), dispc->vid2_fir_coef_hv3);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,4), dispc->vid2_fir_coef_hv4);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,5), dispc->vid2_fir_coef_hv5);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,6), dispc->vid2_fir_coef_hv6);
		dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,7), dispc->vid2_fir_coef_hv7);

		dispc_reg_out(DISPC_VID_CONV_COEF0(v2), dispc->vid2_conv_coef0);
		dispc_reg_out(DISPC_VID_CONV_COEF1(v2), dispc->vid2_conv_coef1);
		dispc_reg_out(DISPC_VID_CONV_COEF2(v2), dispc->vid2_conv_coef2);
		dispc_reg_out(DISPC_VID_CONV_COEF3(v2), dispc->vid2_conv_coef3);
		dispc_reg_out(DISPC_VID_CONV_COEF4(v2), dispc->vid2_conv_coef4);
	break;
	}
}

/*
 * Sync Lost interrupt handler
 */
static void
omap2_synclost_isr(void *arg, struct pt_regs *regs, u32 irqstatus)
{
	int i=0;
	printk(KERN_WARNING "Sync Lost LCD %x\n",dispc_reg_in(DISPC_IRQSTATUS));
	arg = NULL; regs = NULL;

	/*
	 * Disable and Clear all the interrupts before we start
	 */
	dispc_reg_out(DISPC_IRQENABLE, 0x00000000);
	dispc_reg_out(DISPC_IRQSTATUS, 0x0000FFFF);

	/* disable the display controller */
	omap2_disp_disable(HZ/5);

	/*
	 * Update the state of the display controller.
	 */
	dss_ctx.dispc.sysconfig &= ~DISPC_SYSCONFIG_SOFTRESET;
	dss_ctx.dispc.control   &= ~(DISPC_CONTROL_GODIGITAL |
				     DISPC_CONTROL_GOLCD);

        i = 0;

        dispc_reg_out(DISPC_SYSCONFIG, DISPC_SYSCONFIG_SOFTRESET);
        while (!(dispc_reg_in(DISPC_SYSSTATUS) & DISPC_SYSSTATUS_RESETDONE)) {
                udelay (100);
                if (i++ > 5)
                {
                        printk(KERN_WARNING "Failed to soft reset the DSS !! \n");
                        break;
                }
        }

	/* Configure the VENC for the default standard */
	if ((omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV) ||
            (omap2_disp_get_output_dev(OMAP2_VIDEO1) == OMAP2_OUTPUT_TV) ||
            (omap2_disp_get_output_dev(OMAP2_VIDEO2) == OMAP2_OUTPUT_TV)){
		omap2_disp_set_tvstandard(NTSC_M);
	}

	/* Restore the registers */
	omap2_disp_restore_ctx(OMAP_DSS_DISPC_GENERIC);
	omap2_disp_restore_ctx(OMAP2_GRAPHICS);
	omap2_disp_restore_ctx(OMAP2_VIDEO1);
	omap2_disp_restore_ctx(OMAP2_VIDEO2);

	/* enable the display controller */
	if (layer[OMAP_DSS_DISPC_GENERIC].ctx_valid)
		dispc_reg_out(DISPC_CONTROL, dss_ctx.dispc.control);

	omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
	if ((omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV) ||
            (omap2_disp_get_output_dev(OMAP2_VIDEO1) == OMAP2_OUTPUT_TV) ||
            (omap2_disp_get_output_dev(OMAP2_VIDEO2) == OMAP2_OUTPUT_TV)){
		omap2_disp_reg_sync(OMAP2_OUTPUT_TV);
	}
}

static inline u32
pages_per_side(u32 img_side, u32 page_exp)
{
	/*  page_side = 2 ^ page_exp
	 * (page_side - 1) is added for rounding up
	 */
	return (u32) (img_side + (1<<page_exp) - 1) >> page_exp;
}

int omap2_disp_get_vrfb_offset(u32 img_len, u32 bytes_per_pixel,int side)
{
	int page_width_exp, page_height_exp, pixel_size_exp,offset =0;
	
	/* Maximum supported is 4 bytes (RGB32) */
	if (bytes_per_pixel > 4)
		return -EINVAL;

	page_width_exp  = PAGE_WIDTH_EXP;
	page_height_exp = PAGE_HEIGHT_EXP;
	pixel_size_exp  = bytes_per_pixel >> 1;
	
	if(side == SIDE_W) {
		offset = ((1<<page_width_exp) * (pages_per_side(img_len * 
				bytes_per_pixel, page_width_exp))) >> 
			pixel_size_exp;	/* in pixels */
	} else {
		offset = (1<<page_height_exp) *
		 (pages_per_side(img_len, page_height_exp));
	}	
	
	return (offset);
}

void omap2_disp_set_addr(int ltype, u32 lcd_phys_addr, u32 tv_phys_addr_f0, 
		u32 tv_phys_addr_f1)
{
	int v=0;
	v = (ltype == OMAP2_VIDEO1)?0:1;
	layer[ltype].dma[0].ba0 = lcd_phys_addr;
	layer[ltype].dma[0].ba1 = lcd_phys_addr;

	/*
	 * Store BA0 BA1 for TV, BA1 points to the alternate row
	 */
	layer[ltype].dma[1].ba0 = tv_phys_addr_f0;
	layer[ltype].dma[1].ba1 = tv_phys_addr_f1;
	dispc_reg_out(DISPC_VID_BA0(v), tv_phys_addr_f0);

	if (omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV){
		dispc_reg_out(DISPC_VID_BA0(v), layer[ltype].dma[1].ba0);
		dispc_reg_out(DISPC_VID_BA1(v), layer[ltype].dma[1].ba1);
		dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
				DISPC_VID_ATTRIBUTES_ENABLE,
				DISPC_VID_ATTRIBUTES_ENABLE);
		dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GODIGITAL,
				DISPC_CONTROL_GODIGITAL);
	} else {
		dispc_reg_out(DISPC_VID_BA0(v), layer[ltype].dma[0].ba0);
		dispc_reg_out(DISPC_VID_BA1(v), layer[ltype].dma[0].ba1);
		dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
				DISPC_VID_ATTRIBUTES_ENABLE,
				DISPC_VID_ATTRIBUTES_ENABLE);
		dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
				DISPC_CONTROL_GOLCD);
	}