lib_at91sam9260.h

This software package contains the USB framework core developped by ATMEL, as well as a Mass stora

{
        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}

/* *****************************************************************************
                SOFTWARE API FOR PMC
   ***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgSysClkEnableReg
//* \brief Configure the System Clock Enable Register of the PMC controller
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgSysClkEnableReg (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int mode)
{
	//* Write to the SCER register
	pPMC->PMC_SCER = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgSysClkDisableReg
//* \brief Configure the System Clock Disable Register of the PMC controller
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgSysClkDisableReg (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int mode) 
{
	//* Write to the SCDR register
	pPMC->PMC_SCDR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetSysClkStatusReg
//* \brief Return the System Clock Status Register of the PMC controller
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
	AT91PS_PMC pPMC // pointer to a CAN controller
	)
{
	return pPMC->PMC_SCSR;	
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_EnableHCK
//* \brief Enable AHB peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_EnableHCK (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int hck) // \arg AHB peripheral clock identifier
{
	pPMC->PMC_SCER = (1 << hck) << 16;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_DisableHCK
//* \brief Disable AHB peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_DisableHCK (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int hck) // \arg AHB peripheral clock identifier
{
	pPMC->PMC_SCDR = (1 << hck) << 16;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_EnablePeriphClock
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_EnablePeriphClock (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int periphIds)  // \arg IDs of peripherals
{
	pPMC->PMC_PCER = periphIds;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_DisablePeriphClock
//* \brief Disable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_DisablePeriphClock (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int periphIds)  // \arg IDs of peripherals
{
	pPMC->PMC_PCDR = periphIds;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetPeriphClock
//* \brief Get peripheral clock status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetPeriphClock (
	AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
	return pPMC->PMC_PCSR;	
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgMainOscillatorReg (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int mode)
{
	pCKGR->CKGR_MOR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	return pCKGR->CKGR_MOR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_EnableMainOscillator
//* \brief Enable the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_EnableMainOscillator(
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisableMainOscillator
//* \brief Disable the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisableMainOscillator (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
//* \brief Cfg MOR Register according to the main osc startup time
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgMainOscStartUpTime (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
	unsigned int slowClock)  // \arg slowClock in Hz
{
	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainClockFreqReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	return pCKGR->CKGR_MCFR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetMainClock
//* \brief Return Main clock in Hz
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainClock (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgPLLAReg
//* \brief Cfg the PLLA Register
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgPLLAReg (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int mode)
{
	pCKGR->CKGR_PLLAR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetPLLAReg
//* \brief Get the PLLA Register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetPLLAReg (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	return pCKGR->CKGR_PLLAR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgPLLBReg
//* \brief Cfg the PLLB Register
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgPLLBReg (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int mode)
{
	pCKGR->CKGR_PLLBR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_GetPLLBReg
//* \brief Get the PLLB Register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetPLLBReg (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	return pCKGR->CKGR_PLLBR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgPLLA_TransientTime
//* \brief Cfg PLL oscount field according to the PLL transient time
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgPLLA_TransientTime (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int transient_time,  // \arg PLL transient time in microsecond (us)
	unsigned int slowClock)  // \arg slowClock in Hz
{
	pCKGR->CKGR_PLLAR &= ~AT91C_CKGR_PLLACOUNT;
	pCKGR->CKGR_PLLAR |= ((slowClock * transient_time)/1000000) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_CfgPLLB_TransientTime
//* \brief Cfg PLL oscount field according to the PLL transient time
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgPLLB_TransientTime (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int transient_time,  // \arg PLL transient time in microsecond (us)
	unsigned int slowClock)  // \arg slowClock in Hz
{
	pCKGR->CKGR_PLLBR &= ~AT91C_CKGR_PLLBCOUNT;
	pCKGR->CKGR_PLLBR |= ((slowClock * transient_time)/1000000) << 8;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLAOutput
//* \brief Disable the PLLA output
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLAOutput (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLAR &= ~AT91C_CKGR_MULA;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLBOutput
//* \brief Disable the PLLB output
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLBOutput (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLBR &= ~AT91C_CKGR_MULB;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLAInput
//* \brief Disable the PLLA Input
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLAInput (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLAR &= ~AT91C_CKGR_DIVA;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLBInput
//* \brief Disable the PLLB Input
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLBInput (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLBR &= ~AT91C_CKGR_DIVB;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLA
//* \brief Disable the PLLA input and output for conso reduction
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLA (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLAR &= ~(AT91C_CKGR_MULA|AT91C_CKGR_DIVA);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_CKGR_DisablePLLB
//* \brief Disable the PLLB input and output for conso reduction
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisablePLLB (
	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
	pCKGR->CKGR_PLLBR &= ~(AT91C_CKGR_MULB|AT91C_CKGR_DIVB);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_CfgMCKReg
//* \brief Cfg Master Clock Register
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgMCKReg (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	unsigned int mode)
{
	pPMC->PMC_MCKR = mode;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetMCKReg
//* \brief Return Master Clock Register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetMCKReg(
	AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
	return pPMC->PMC_MCKR;
}

//*--------