1.sim.rpt

一个不错的ROM例子

; |ram_32|ram_initial~335                                                    ; |ram_32|ram_initial~335                                                    ; out              ;
; |ram_32|ram_initial~336                                                    ; |ram_32|ram_initial~336                                                    ; out              ;
; |ram_32|ram_initial~337                                                    ; |ram_32|ram_initial~337                                                    ; out              ;
; |ram_32|ram_initial~338                                                    ; |ram_32|ram_initial~338                                                    ; out              ;
; |ram_32|ram_initial~339                                                    ; |ram_32|ram_initial~339                                                    ; out              ;
; |ram_32|ram_initial~341                                                    ; |ram_32|ram_initial~341                                                    ; out              ;
; |ram_32|ram_initial~343                                                    ; |ram_32|ram_initial~343                                                    ; out              ;
; |ram_32|ram_initial~344                                                    ; |ram_32|ram_initial~344                                                    ; out              ;
; |ram_32|ram_initial~345                                                    ; |ram_32|ram_initial~345                                                    ; out              ;
; |ram_32|ram_initial~346                                                    ; |ram_32|ram_initial~346                                                    ; out              ;
; |ram_32|ram_initial~348                                                    ; |ram_32|ram_initial~348                                                    ; out              ;
; |ram_32|ram_initial~349                                                    ; |ram_32|ram_initial~349                                                    ; out              ;
; |ram_32|ram_initial~350                                                    ; |ram_32|ram_initial~350                                                    ; out              ;
; |ram_32|ram_initial~351                                                    ; |ram_32|ram_initial~351                                                    ; out              ;
; |ram_32|ram_initial~354                                                    ; |ram_32|ram_initial~354                                                    ; out              ;
; |ram_32|ram_initial~355                                                    ; |ram_32|ram_initial~355                                                    ; out              ;
; |ram_32|ram_initial~357                                                    ; |ram_32|ram_initial~357                                                    ; out              ;
; |ram_32|ram_initial~359                                                    ; |ram_32|ram_initial~359                                                    ; out              ;
; |ram_32|ram_initial~360                                                    ; |ram_32|ram_initial~360                                                    ; out              ;
; |ram_32|ram_initial~362                                                    ; |ram_32|ram_initial~362                                                    ; out              ;
; |ram_32|ram_initial~366                                                    ; |ram_32|ram_initial~366                                                    ; out              ;
; |ram_32|ram_initial~367                                                    ; |ram_32|ram_initial~367                                                    ; out              ;
; |ram_32|ram_initial~368                                                    ; |ram_32|ram_initial~368                                                    ; out              ;
; |ram_32|ram_initial~371                                                    ; |ram_32|ram_initial~371                                                    ; out              ;
; |ram_32|ram_initial~375                                                    ; |ram_32|ram_initial~375                                                    ; out              ;
; |ram_32|ram_initial~376                                                    ; |ram_32|ram_initial~376                                                    ; out              ;
; |ram_32|ram_initial~378                                                    ; |ram_32|ram_initial~378                                                    ; out              ;
; |ram_32|ram_initial~380                                                    ; |ram_32|ram_initial~380                                                    ; out              ;
; |ram_32|ram_initial~382                                                    ; |ram_32|ram_initial~382                                                    ; out              ;
; |ram_32|ram_initial~383                                                    ; |ram_32|ram_initial~383                                                    ; out              ;
; |ram_32|ram_initial~384                                                    ; |ram_32|ram_initial~384                                                    ; out              ;
; |ram_32|ram_initial~385                                                    ; |ram_32|ram_initial~385                                                    ; out              ;
; |ram_32|ram_initial~386                                                    ; |ram_32|ram_initial~386                                                    ; out              ;
; |ram_32|ram_initial~387                                                    ; |ram_32|ram_initial~387                                                    ; out              ;
; |ram_32|ram_initial~389                                                    ; |ram_32|ram_initial~389                                                    ; out              ;
; |ram_32|ram_initial~391                                                    ; |ram_32|ram_initial~391                                                    ; out              ;
; |ram_32|ram_initial~394                                                    ; |ram_32|ram_initial~394                                                    ; out              ;
; |ram_32|ram_initial~396                                                    ; |ram_32|ram_initial~396                                                    ; out              ;
; |ram_32|ram_initial~398                                                    ; |ram_32|ram_initial~398                                                    ; out              ;
; |ram_32|ram_initial~432                                                    ; |ram_32|ram_initial~432                                                    ; out0             ;
; |ram_32|ram_initial~433                                                    ; |ram_32|ram_initial~433                                                    ; out0             ;
; |ram_32|ram_initial~434                                                    ; |ram_32|ram_initial~434                                                    ; out0             ;
; |ram_32|ram_initial~435                                                    ; |ram_32|ram_initial~435                                                    ; out0             ;
; |ram_32|ram_initial~436                                                    ; |ram_32|ram_initial~436                                                    ; out0             ;
; |ram_32|ram_initial~437                                                    ; |ram_32|ram_initial~437                                                    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~0              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~0              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|result_node[0]~1 ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|result_node[0]~1 ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|result_node[0]   ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|result_node[0]   ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~2              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~2              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~3              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~3              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~4              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~4              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result36w~1    ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result36w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result36w      ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result36w      ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~6              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~6              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~7              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~7              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~8              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~8              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~9              ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~9              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~11             ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~11             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~12             ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~12             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result44w~1    ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result44w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result44w      ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result44w      ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~13             ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~13             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~15             ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~15             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~16             ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|_~16             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result65w~1    ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result65w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result65w      ; |ram_32|lpm_mux:ram_initial_rtl_15|mux_jcc:auto_generated|w_result65w      ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]~0 ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]~0 ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~0              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~0              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]~1 ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]~1 ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]   ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|result_node[0]   ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~1              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~1              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~2              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~2              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w~0    ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w~0    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~3              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~3              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~4              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~4              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w~1    ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w      ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result36w      ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~5              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~5              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~6              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~6              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w~0    ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w~0    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~7              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~7              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w~1    ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w      ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result37w      ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~9              ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~9              ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~11             ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~11             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~12             ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|_~12             ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result44w~1    ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result44w~1    ; out0             ;
; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result44w      ; |ram_32|lpm_mux:ram_initial_rtl_14|mux_jcc:auto_generated|w_result44w      ; out0             ;