1.fnsim.qmsg

一个不错的ROM例子

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 20:16:45 2009 " "Info: Processing started: Sun Jan 11 20:16:45 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 1 -c 1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 1 -c 1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram_32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram_32-rtl " "Info: Found design unit 1: ram_32-rtl" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram_32 " "Info: Found entity 1: ram_32" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram_32 " "Info: Elaborating entity \"ram_32\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "d:/quartus2.0/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:ram_initial_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_mux:ram_initial_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_jcc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_jcc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_jcc " "Info: Found entity 1: mux_jcc" {  } { { "db/mux_jcc.tdf" "" { Text "D:/Quartus2.0/22ram/db/mux_jcc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 20:16:47 2009 " "Info: Processing ended: Sun Jan 11 20:16:47 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}