1.tan.qmsg

一个不错的ROM例子

{ "Info" "ITDB_FULL_TCO_RESULT" "wr dout\[3\] ram_initial~158 12.947 ns register " "Info: tco from clock \"wr\" to destination pin \"dout\[3\]\" through register \"ram_initial~158\" is 12.947 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr 1 CLK PIN_17 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 128; CLK Node = 'wr'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ram_initial~158 2 REG LC_X20_Y11_N3 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y11_N3; Fanout = 1; REG Node = 'ram_initial~158'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.313 ns" { wr ram_initial~158 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~158 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~158 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.941 ns + Longest register pin " "Info: + Longest register to pin delay is 9.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_initial~158 1 REG LC_X20_Y11_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N3; Fanout = 1; REG Node = 'ram_initial~158'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { ram_initial~158 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.442 ns) 1.697 ns ram_initial~4127 2 COMB LC_X20_Y9_N9 1 " "Info: 2: + IC(1.255 ns) + CELL(0.442 ns) = 1.697 ns; Loc. = LC_X20_Y9_N9; Fanout = 1; COMB Node = 'ram_initial~4127'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.697 ns" { ram_initial~158 ram_initial~4127 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.442 ns) 3.334 ns ram_initial~4128 3 COMB LC_X20_Y12_N2 1 " "Info: 3: + IC(1.195 ns) + CELL(0.442 ns) = 3.334 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; COMB Node = 'ram_initial~4128'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.637 ns" { ram_initial~4127 ram_initial~4128 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.590 ns) 5.139 ns ram_initial~4131 4 COMB LC_X19_Y11_N9 1 " "Info: 4: + IC(1.215 ns) + CELL(0.590 ns) = 5.139 ns; Loc. = LC_X19_Y11_N9; Fanout = 1; COMB Node = 'ram_initial~4131'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.805 ns" { ram_initial~4128 ram_initial~4131 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.678 ns) + CELL(2.124 ns) 9.941 ns dout\[3\] 5 PIN PIN_84 0 " "Info: 5: + IC(2.678 ns) + CELL(2.124 ns) = 9.941 ns; Loc. = PIN_84; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "4.802 ns" { ram_initial~4131 dout[3] } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.598 ns ( 36.19 % ) " "Info: Total cell delay = 3.598 ns ( 36.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.343 ns ( 63.81 % ) " "Info: Total interconnect delay = 6.343 ns ( 63.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "9.941 ns" { ram_initial~158 ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "9.941 ns" { ram_initial~158 ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } { 0.000ns 1.255ns 1.195ns 1.215ns 2.678ns } { 0.000ns 0.442ns 0.442ns 0.590ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~158 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~158 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "9.941 ns" { ram_initial~158 ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "9.941 ns" { ram_initial~158 ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } { 0.000ns 1.255ns 1.195ns 1.215ns 2.678ns } { 0.000ns 0.442ns 0.442ns 0.590ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] dout\[3\] 16.025 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"dout\[3\]\" is 16.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a\[1\] 1 PIN PIN_114 56 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_114; Fanout = 56; PIN Node = 'a\[1\]'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.716 ns) + CELL(0.590 ns) 7.781 ns ram_initial~4127 2 COMB LC_X20_Y9_N9 1 " "Info: 2: + IC(5.716 ns) + CELL(0.590 ns) = 7.781 ns; Loc. = LC_X20_Y9_N9; Fanout = 1; COMB Node = 'ram_initial~4127'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "6.306 ns" { a[1] ram_initial~4127 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.442 ns) 9.418 ns ram_initial~4128 3 COMB LC_X20_Y12_N2 1 " "Info: 3: + IC(1.195 ns) + CELL(0.442 ns) = 9.418 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; COMB Node = 'ram_initial~4128'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.637 ns" { ram_initial~4127 ram_initial~4128 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.590 ns) 11.223 ns ram_initial~4131 4 COMB LC_X19_Y11_N9 1 " "Info: 4: + IC(1.215 ns) + CELL(0.590 ns) = 11.223 ns; Loc. = LC_X19_Y11_N9; Fanout = 1; COMB Node = 'ram_initial~4131'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.805 ns" { ram_initial~4128 ram_initial~4131 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.678 ns) + CELL(2.124 ns) 16.025 ns dout\[3\] 5 PIN PIN_84 0 " "Info: 5: + IC(2.678 ns) + CELL(2.124 ns) = 16.025 ns; Loc. = PIN_84; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "4.802 ns" { ram_initial~4131 dout[3] } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.221 ns ( 32.58 % ) " "Info: Total cell delay = 5.221 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.804 ns ( 67.42 % ) " "Info: Total interconnect delay = 10.804 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "16.025 ns" { a[1] ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "16.025 ns" { a[1] a[1]~out0 ram_initial~4127 ram_initial~4128 ram_initial~4131 dout[3] } { 0.000ns 0.000ns 5.716ns 1.195ns 1.215ns 2.678ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.590ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ram_initial~110 din\[11\] wr -3.824 ns register " "Info: th for register \"ram_initial~110\" (data pin = \"din\[11\]\", clock pin = \"wr\") is -3.824 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr 1 CLK PIN_17 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 128; CLK Node = 'wr'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ram_initial~110 2 REG LC_X23_Y9_N9 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X23_Y9_N9; Fanout = 1; REG Node = 'ram_initial~110'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.313 ns" { wr ram_initial~110 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~110 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~110 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.621 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.621 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns din\[11\] 1 PIN PIN_98 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_98; Fanout = 8; PIN Node = 'din\[11\]'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { din[11] } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.037 ns) + CELL(0.115 ns) 6.621 ns ram_initial~110 2 REG LC_X23_Y9_N9 1 " "Info: 2: + IC(5.037 ns) + CELL(0.115 ns) = 6.621 ns; Loc. = LC_X23_Y9_N9; Fanout = 1; REG Node = 'ram_initial~110'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "5.152 ns" { din[11] ram_initial~110 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.92 % ) " "Info: Total cell delay = 1.584 ns ( 23.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.037 ns ( 76.08 % ) " "Info: Total interconnect delay = 5.037 ns ( 76.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "6.621 ns" { din[11] ram_initial~110 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "6.621 ns" { din[11] din[11]~out0 ram_initial~110 } { 0.000ns 0.000ns 5.037ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~110 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~110 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "6.621 ns" { din[11] ram_initial~110 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "6.621 ns" { din[11] din[11]~out0 ram_initial~110 } { 0.000ns 0.000ns 5.037ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 20:08:54 2009 " "Info: Processing ended: Sun Jan 11 20:08:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}