1.tan.qmsg

一个不错的ROM例子

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 20:08:53 2009 " "Info: Processing started: Sun Jan 11 20:08:53 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 1 -c 1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 1 -c 1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "wr " "Info: Assuming node \"wr\" is an undefined clock" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 11 -1 0 } } { "d:/quartus2.0/win/Assignment Editor.qase" "" { Assignment "d:/quartus2.0/win/Assignment Editor.qase" 1 { { 0 "wr" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "wr " "Info: No valid register-to-register data paths exist for clock \"wr\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ram_initial~210 a\[2\] wr 8.336 ns register " "Info: tsu for register \"ram_initial~210\" (data pin = \"a\[2\]\", clock pin = \"wr\") is 8.336 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.081 ns + Longest pin register " "Info: + Longest pin to register delay is 11.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a\[2\] 1 PIN PIN_112 24 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_112; Fanout = 24; PIN Node = 'a\[2\]'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.064 ns) + CELL(0.590 ns) 8.129 ns rtl~4 2 COMB LC_X19_Y11_N7 16 " "Info: 2: + IC(6.064 ns) + CELL(0.590 ns) = 8.129 ns; Loc. = LC_X19_Y11_N7; Fanout = 16; COMB Node = 'rtl~4'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "6.654 ns" { a[2] rtl~4 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.085 ns) + CELL(0.867 ns) 11.081 ns ram_initial~210 3 REG LC_X23_Y10_N6 1 " "Info: 3: + IC(2.085 ns) + CELL(0.867 ns) = 11.081 ns; Loc. = LC_X23_Y10_N6; Fanout = 1; REG Node = 'ram_initial~210'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.952 ns" { rtl~4 ram_initial~210 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.932 ns ( 26.46 % ) " "Info: Total cell delay = 2.932 ns ( 26.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.149 ns ( 73.54 % ) " "Info: Total interconnect delay = 8.149 ns ( 73.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "11.081 ns" { a[2] rtl~4 ram_initial~210 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "11.081 ns" { a[2] a[2]~out0 rtl~4 ram_initial~210 } { 0.000ns 0.000ns 6.064ns 2.085ns } { 0.000ns 1.475ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"wr\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr 1 CLK PIN_17 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 128; CLK Node = 'wr'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ram_initial~210 2 REG LC_X23_Y10_N6 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X23_Y10_N6; Fanout = 1; REG Node = 'ram_initial~210'" {  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "1.313 ns" { wr ram_initial~210 } "NODE_NAME" } } { "ram_32.vhd" "" { Text "D:/Quartus2.0/22ram/ram_32.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~210 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~210 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "11.081 ns" { a[2] rtl~4 ram_initial~210 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "11.081 ns" { a[2] a[2]~out0 rtl~4 ram_initial~210 } { 0.000ns 0.000ns 6.064ns 2.085ns } { 0.000ns 1.475ns 0.590ns 0.867ns } } } { "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2.0/win/TimingClosureFloorplan.fld" "" "2.782 ns" { wr ram_initial~210 } "NODE_NAME" } } { "d:/quartus2.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2.0/win/Technology_Viewer.qrui" "2.782 ns" { wr wr~out0 ram_initial~210 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}