ram_32.vhd

一个不错的ROM例子

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

entity  ram_32 is
port( a:in std_logic_vector(7 downto 0);
     din:in std_logic_vector(15 downto 0);
      cs:in std_logic;
      rd:in std_logic;
      wr:in std_logic;
      dout:out std_logic_vector(15 downto 0));
end ram_32;
 
architecture rtl of ram_32 is
subtype rom_word is std_logic_vector(15 downto 0);
type  memory is array(0 to 7) of rom_word;
signal ram_initial:memory:=(
        (x"0000"),(x"1021"),(x"2042"),(x"3063"),
        (x"4084"),(x"50a5"),(x"60c6"),(x"70e7"));
begin
process(wr)
begin
if(wr 'event and wr='1')then
if(cs='1')then
ram_initial(conv_integer(a))<=din;
end if;
end if;
end process;
process(cs,rd,a,ram_initial)
begin
if(cs='1' and rd='0')then
dout<=ram_initial(conv_integer(a));
else
dout<=(others=>'Z');
end if;
end process;
end rtl;