uc_interface_timesim.vhd

8051接口VHDL代码

      I1 => GND,
      O => dataout_en_MC_D2
    );
  dataout_en_MC_XOR : X_XOR2
    port map (
      I0 => dataout_en_MC_D1,
      I1 => dataout_en_MC_D2,
      O => dataout_en_MC_D
    );
  address_low_0_Q : X_BUF
    port map (
      I => address_low_0_MC_Q,
      O => address_low(0)
    );
  address_low_0_MC_R_OR_PRLD_60 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_0_MC_R_OR_PRLD
    );
  address_low_0_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_0_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_0_MC_R_OR_PRLD,
      O => address_low_0_MC_Q
    );
  ale_n_II_FCLK_tsimcreated_inv_Q_61 : X_INV
    port map (
      I => ale_n_II_FCLK,
      O => ale_n_II_FCLK_tsimcreated_inv_Q
    );
  address_low_0_MC_D1_PT_0_62 : X_AND2
    port map (
      I0 => addr_data_0_II_UIM,
      I1 => addr_data_0_II_UIM,
      O => address_low_0_MC_D1_PT_0
    );
  address_low_0_MC_D1_63 : X_OR2
    port map (
      I0 => address_low_0_MC_D1_PT_0,
      I1 => address_low_0_MC_D1_PT_0,
      O => address_low_0_MC_D1
    );
  address_low_0_MC_D2_64 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_0_MC_D2
    );
  address_low_0_MC_XOR : X_XOR2
    port map (
      I0 => address_low_0_MC_D1,
      I1 => address_low_0_MC_D2,
      O => address_low_0_MC_D
    );
  addr_data_0_II_UIM_65 : X_BUF
    port map (
      I => addr_data(0),
      O => addr_data_0_II_UIM
    );
  address_low_1_Q : X_BUF
    port map (
      I => address_low_1_MC_Q,
      O => address_low(1)
    );
  address_low_1_MC_R_OR_PRLD_66 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_1_MC_R_OR_PRLD
    );
  address_low_1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_1_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_1_MC_R_OR_PRLD,
      O => address_low_1_MC_Q
    );
  address_low_1_MC_D1_PT_0_67 : X_AND2
    port map (
      I0 => addr_data_1_II_UIM,
      I1 => addr_data_1_II_UIM,
      O => address_low_1_MC_D1_PT_0
    );
  address_low_1_MC_D1_68 : X_OR2
    port map (
      I0 => address_low_1_MC_D1_PT_0,
      I1 => address_low_1_MC_D1_PT_0,
      O => address_low_1_MC_D1
    );
  address_low_1_MC_D2_69 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_1_MC_D2
    );
  address_low_1_MC_XOR : X_XOR2
    port map (
      I0 => address_low_1_MC_D1,
      I1 => address_low_1_MC_D2,
      O => address_low_1_MC_D
    );
  addr_data_1_II_UIM_70 : X_BUF
    port map (
      I => addr_data(1),
      O => addr_data_1_II_UIM
    );
  address_low_2_Q : X_BUF
    port map (
      I => address_low_2_MC_Q,
      O => address_low(2)
    );
  address_low_2_MC_R_OR_PRLD_71 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_2_MC_R_OR_PRLD
    );
  address_low_2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_2_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_2_MC_R_OR_PRLD,
      O => address_low_2_MC_Q
    );
  address_low_2_MC_D1_PT_0_72 : X_AND2
    port map (
      I0 => addr_data_2_II_UIM,
      I1 => addr_data_2_II_UIM,
      O => address_low_2_MC_D1_PT_0
    );
  address_low_2_MC_D1_73 : X_OR2
    port map (
      I0 => address_low_2_MC_D1_PT_0,
      I1 => address_low_2_MC_D1_PT_0,
      O => address_low_2_MC_D1
    );
  address_low_2_MC_D2_74 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_2_MC_D2
    );
  address_low_2_MC_XOR : X_XOR2
    port map (
      I0 => address_low_2_MC_D1,
      I1 => address_low_2_MC_D2,
      O => address_low_2_MC_D
    );
  addr_data_2_II_UIM_75 : X_BUF
    port map (
      I => addr_data(2),
      O => addr_data_2_II_UIM
    );
  address_low_3_Q : X_BUF
    port map (
      I => address_low_3_MC_Q,
      O => address_low(3)
    );
  address_low_3_MC_R_OR_PRLD_76 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_3_MC_R_OR_PRLD
    );
  address_low_3_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_3_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_3_MC_R_OR_PRLD,
      O => address_low_3_MC_Q
    );
  address_low_3_MC_D1_PT_0_77 : X_AND2
    port map (
      I0 => addr_data_3_II_UIM,
      I1 => addr_data_3_II_UIM,
      O => address_low_3_MC_D1_PT_0
    );
  address_low_3_MC_D1_78 : X_OR2
    port map (
      I0 => address_low_3_MC_D1_PT_0,
      I1 => address_low_3_MC_D1_PT_0,
      O => address_low_3_MC_D1
    );
  address_low_3_MC_D2_79 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_3_MC_D2
    );
  address_low_3_MC_XOR : X_XOR2
    port map (
      I0 => address_low_3_MC_D1,
      I1 => address_low_3_MC_D2,
      O => address_low_3_MC_D
    );
  addr_data_3_II_UIM_80 : X_BUF
    port map (
      I => addr_data(3),
      O => addr_data_3_II_UIM
    );
  address_low_4_Q : X_BUF
    port map (
      I => address_low_4_MC_Q,
      O => address_low(4)
    );
  address_low_4_MC_R_OR_PRLD_81 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_4_MC_R_OR_PRLD
    );
  address_low_4_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_4_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_4_MC_R_OR_PRLD,
      O => address_low_4_MC_Q
    );
  address_low_4_MC_D1_PT_0_82 : X_AND2
    port map (
      I0 => addr_data_4_II_UIM,
      I1 => addr_data_4_II_UIM,
      O => address_low_4_MC_D1_PT_0
    );
  address_low_4_MC_D1_83 : X_OR2
    port map (
      I0 => address_low_4_MC_D1_PT_0,
      I1 => address_low_4_MC_D1_PT_0,
      O => address_low_4_MC_D1
    );
  address_low_4_MC_D2_84 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_4_MC_D2
    );
  address_low_4_MC_XOR : X_XOR2
    port map (
      I0 => address_low_4_MC_D1,
      I1 => address_low_4_MC_D2,
      O => address_low_4_MC_D
    );
  addr_data_4_II_UIM_85 : X_BUF
    port map (
      I => addr_data(4),
      O => addr_data_4_II_UIM
    );
  address_low_5_Q : X_BUF
    port map (
      I => address_low_5_MC_Q,
      O => address_low(5)
    );
  address_low_5_MC_R_OR_PRLD_86 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_5_MC_R_OR_PRLD
    );
  address_low_5_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_5_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_5_MC_R_OR_PRLD,
      O => address_low_5_MC_Q
    );
  address_low_5_MC_D1_PT_0_87 : X_AND2
    port map (
      I0 => addr_data_5_II_UIM,
      I1 => addr_data_5_II_UIM,
      O => address_low_5_MC_D1_PT_0
    );
  address_low_5_MC_D1_88 : X_OR2
    port map (
      I0 => address_low_5_MC_D1_PT_0,
      I1 => address_low_5_MC_D1_PT_0,
      O => address_low_5_MC_D1
    );
  address_low_5_MC_D2_89 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => address_low_5_MC_D2
    );
  address_low_5_MC_XOR : X_XOR2
    port map (
      I0 => address_low_5_MC_D1,
      I1 => address_low_5_MC_D2,
      O => address_low_5_MC_D
    );
  addr_data_5_II_UIM_90 : X_BUF
    port map (
      I => addr_data(5),
      O => addr_data_5_II_UIM
    );
  address_low_6_Q : X_BUF
    port map (
      I => address_low_6_MC_Q,
      O => address_low(6)
    );
  address_low_6_MC_R_OR_PRLD_91 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => address_low_6_MC_R_OR_PRLD
    );
  address_low_6_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => address_low_6_MC_D,
      CE => VCC,
      CLK => ale_n_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => address_low_6_MC_R_OR_PRLD,
      O => address_low_6_MC_Q
    );
  address_low_6_MC_D1_PT_0_92 : X_AND2
    port map (
      I0 => addr_data_6_II_UIM,
      I1 => addr_data_6_II_UIM,
      O => address_low_6_MC_D1_PT_0
    );