uc_interface_timesim.vhd

8051接口VHDL代码

      I3 => wr_n_II_UIM,
      O => prs_state_fft1_MC_D2_PT_1
    );
  prs_state_fft1_MC_D2_PT_2_19 : X_AND4
    port map (
      I0 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN1,
      I2 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN2,
      I3 => psen_n_II_UIM,
      O => prs_state_fft1_MC_D2_PT_2
    );
  prs_state_fft1_MC_D2_20 : X_OR3
    port map (
      I0 => prs_state_fft1_MC_D2_PT_0,
      I1 => prs_state_fft1_MC_D2_PT_1,
      I2 => prs_state_fft1_MC_D2_PT_2,
      O => prs_state_fft1_MC_D2
    );
  prs_state_fft1_MC_D_21 : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D_TFF,
      I1 => prs_state_fft1_MC_Q,
      O => prs_state_fft1_MC_D
    );
  prs_state_fft1_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D1,
      I1 => prs_state_fft1_MC_D2,
      O => prs_state_fft1_MC_D_TFF
    );
  prs_state_fft2_22 : X_BUF
    port map (
      I => prs_state_fft2_MC_Q,
      O => prs_state_fft2
    );
  prs_state_fft2_MC_R_OR_PRLD_23 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => prs_state_fft2_MC_R_OR_PRLD
    );
  prs_state_fft2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft2_MC_R_OR_PRLD,
      O => prs_state_fft2_MC_Q
    );
  prs_state_fft2_MC_D1_24 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft2_MC_D1
    );
  prs_state_fft2_MC_D2_PT_0_25 : X_AND3
    port map (
      I0 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_0_IN0,
      I1 => prs_state_fft2,
      I2 => ale_n_II_UIM,
      O => prs_state_fft2_MC_D2_PT_0
    );
  prs_state_fft2_MC_D2_PT_1_26 : X_AND4
    port map (
      I0 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN2,
      I3 => addr_match,
      O => prs_state_fft2_MC_D2_PT_1
    );
  prs_state_fft2_MC_D2_PT_2_27 : X_AND4
    port map (
      I0 => prs_state_fft1,
      I1 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_2_IN1,
      I2 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_2_IN2,
      I3 => addr_match,
      O => prs_state_fft2_MC_D2_PT_2
    );
  prs_state_fft2_MC_D2_28 : X_OR3
    port map (
      I0 => prs_state_fft2_MC_D2_PT_0,
      I1 => prs_state_fft2_MC_D2_PT_1,
      I2 => prs_state_fft2_MC_D2_PT_2,
      O => prs_state_fft2_MC_D2
    );
  prs_state_fft2_MC_D_29 : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D_TFF,
      I1 => prs_state_fft2_MC_Q,
      O => prs_state_fft2_MC_D
    );
  prs_state_fft2_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D1,
      I1 => prs_state_fft2_MC_D2,
      O => prs_state_fft2_MC_D_TFF
    );
  ale_n_II_UIM_30 : X_BUF
    port map (
      I => ale_n,
      O => ale_n_II_UIM
    );
  ale_n_II_FCLK_31 : X_BUF
    port map (
      I => ale_n,
      O => ale_n_II_FCLK
    );
  addr_match_32 : X_BUF
    port map (
      I => addr_match_MC_Q,
      O => addr_match
    );
  addr_match_MC_R_OR_PRLD_33 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => addr_match_MC_R_OR_PRLD
    );
  addr_match_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => addr_match_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => addr_match_MC_R_OR_PRLD,
      O => addr_match_MC_Q
    );
  addr_match_MC_D1_PT_0_34 : X_AND16
    port map (
      I0 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN1,
      I2 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN2,
      I3 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN3,
      I4 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN4,
      I5 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN5,
      I6 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN6,
      I7 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN7,
      I8 => NlwInverterSignal_addr_match_MC_D1_PT_0_IN8,
      I9 => psen_n_II_UIM,
      I10 => VCC,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => addr_match_MC_D1_PT_0
    );
  addr_match_MC_D1_35 : X_OR2
    port map (
      I0 => addr_match_MC_D1_PT_0,
      I1 => addr_match_MC_D1_PT_0,
      O => addr_match_MC_D1
    );
  addr_match_MC_D2_36 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => addr_match_MC_D2
    );
  addr_match_MC_XOR : X_XOR2
    port map (
      I0 => addr_match_MC_D1,
      I1 => addr_match_MC_D2,
      O => addr_match_MC_D
    );
  addr_0_II_UIM_37 : X_BUF
    port map (
      I => addr(0),
      O => addr_0_II_UIM
    );
  addr_1_II_UIM_38 : X_BUF
    port map (
      I => addr(1),
      O => addr_1_II_UIM
    );
  addr_2_II_UIM_39 : X_BUF
    port map (
      I => addr(2),
      O => addr_2_II_UIM
    );
  addr_3_II_UIM_40 : X_BUF
    port map (
      I => addr(3),
      O => addr_3_II_UIM
    );
  addr_4_II_UIM_41 : X_BUF
    port map (
      I => addr(4),
      O => addr_4_II_UIM
    );
  addr_5_II_UIM_42 : X_BUF
    port map (
      I => addr(5),
      O => addr_5_II_UIM
    );
  addr_6_II_UIM_43 : X_BUF
    port map (
      I => addr(6),
      O => addr_6_II_UIM
    );
  addr_7_II_UIM_44 : X_BUF
    port map (
      I => addr(7),
      O => addr_7_II_UIM
    );
  psen_n_II_UIM_45 : X_BUF
    port map (
      I => psen_n,
      O => psen_n_II_UIM
    );
  clk_II_FCLK_46 : X_BUF
    port map (
      I => clk,
      O => clk_II_FCLK
    );
  wr_n_II_UIM_47 : X_BUF
    port map (
      I => wr_n,
      O => wr_n_II_UIM
    );
  addr_data_0_MC_BUFOE : X_BUF
    port map (
      I => FOOBAR1_ctinst_7,
      O => addr_data_0_MC_BUFOE_OUT
    );
  N_PZ_236_48 : X_BUF
    port map (
      I => N_PZ_236_MC_Q,
      O => N_PZ_236
    );
  N_PZ_236_MC_REG : X_BUF
    port map (
      I => N_PZ_236_MC_D,
      O => N_PZ_236_MC_Q
    );
  N_PZ_236_MC_D1_49 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_236_MC_D1
    );
  N_PZ_236_MC_D2_PT_0_50 : X_AND2
    port map (
      I0 => rd_n_II_UIM,
      I1 => rd_n_II_UIM,
      O => N_PZ_236_MC_D2_PT_0
    );
  N_PZ_236_MC_D2_PT_1_51 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_236_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_N_PZ_236_MC_D2_PT_1_IN1,
      O => N_PZ_236_MC_D2_PT_1
    );
  N_PZ_236_MC_D2_PT_2_52 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_236_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_N_PZ_236_MC_D2_PT_2_IN1,
      O => N_PZ_236_MC_D2_PT_2
    );
  N_PZ_236_MC_D2_PT_3_53 : X_AND4
    port map (
      I0 => NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN0,
      I1 => NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN1,
      I2 => NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN2,
      I3 => NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN3,
      O => N_PZ_236_MC_D2_PT_3
    );
  N_PZ_236_MC_D2_54 : X_OR4
    port map (
      I0 => N_PZ_236_MC_D2_PT_0,
      I1 => N_PZ_236_MC_D2_PT_1,
      I2 => N_PZ_236_MC_D2_PT_2,
      I3 => N_PZ_236_MC_D2_PT_3,
      O => N_PZ_236_MC_D2
    );
  N_PZ_236_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_236_MC_D1,
      I1 => N_PZ_236_MC_D2,
      O => N_PZ_236_MC_D
    );
  dataout_en_55 : X_BUF
    port map (
      I => dataout_en_MC_Q,
      O => dataout_en
    );
  dataout_en_MC_R_OR_PRLD_56 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => dataout_en_MC_R_OR_PRLD
    );
  dataout_en_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dataout_en_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => dataout_en_MC_R_OR_PRLD,
      O => dataout_en_MC_Q
    );
  dataout_en_MC_D1_PT_0_57 : X_AND32
    port map (
      I0 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN1,
      I2 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN2,
      I3 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN3,
      I4 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN4,
      I5 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN5,
      I6 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN6,
      I7 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN7,
      I8 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN8,
      I9 => psen_n_II_UIM,
      I10 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN10,
      I11 => address_low(1),
      I12 => address_low(2),
      I13 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN13,
      I14 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN14,
      I15 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN15,
      I16 => NlwInverterSignal_dataout_en_MC_D1_PT_0_IN16,
      I17 => address_low(7),
      I18 => VCC,
      I19 => VCC,
      I20 => VCC,
      I21 => VCC,
      I22 => VCC,
      I23 => VCC,
      I24 => VCC,
      I25 => VCC,
      I26 => VCC,
      I27 => VCC,
      I28 => VCC,
      I29 => VCC,
      I30 => VCC,
      I31 => VCC,
      O => dataout_en_MC_D1_PT_0
    );
  dataout_en_MC_D1_58 : X_OR2
    port map (
      I0 => dataout_en_MC_D1_PT_0,
      I1 => dataout_en_MC_D1_PT_0,
      O => dataout_en_MC_D1
    );
  dataout_en_MC_D2_59 : X_OR2
    port map (
      I0 => GND,