uc_interface_timesim.vhd

8051接口VHDL代码

  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_stat_en_MC_D1_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_0_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_app_en_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_app_en_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_app_en_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_app_en_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_0_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_0_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_0_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_0_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_1_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_1_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_1_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_1_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_1_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_1_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_1_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_2_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_2_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_2_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_2_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_2_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_2_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_2_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_3_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_3_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_3_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_3_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_3_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_3_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_3_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_3_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_4_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_4_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_4_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_4_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_4_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_4_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_4_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_4_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_4_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ctrl_bits_4_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_5_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_5_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_5_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_5_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_5_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_5_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_status_reg_5_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int_n_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_int_reset_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int_en_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_en_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_int_en_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_int_en_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_start_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_start_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_start_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_start_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_6_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_6_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_6_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_6_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_6_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_6_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_7_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_out_7_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_7_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_7_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_7_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_in_7_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_rdy_reset_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_rdy_reset_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_rdy_reset_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_error_reset_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_need_data_reset_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_need_data_reset_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_need_data_reset_MC_XOR_IN0 : STD_LOGIC; 
  signal data_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal address_low : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal status_reg : STD_LOGIC_VECTOR ( 7 downto 3 ); 
begin
  addr_data_0_Q : X_TRI
    port map (
      I => addr_data_0_MC_Q,
      CTL => addr_data_0_MC_OE,
      O => addr_data(0)
    );
  addr_data_0_MC_Q_0 : X_BUF
    port map (
      I => addr_data_0_MC_Q_tsim_ireg_Q,
      O => addr_data_0_MC_Q
    );
  addr_data_0_MC_R_OR_PRLD_1 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => addr_data_0_MC_R_OR_PRLD
    );
  addr_data_0_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => addr_data_0_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => addr_data_0_MC_R_OR_PRLD,
      O => addr_data_0_MC_Q_tsim_ireg_Q
    );
  VCC_ONE : X_ONE
    port map (
      O => VCC
    );
  FOOBAR3_ctinst_7_2 : X_AND2
    port map (
      I0 => reset_II_UIM,
      I1 => reset_II_UIM,
      O => NlwInverterSignal_FOOBAR3_ctinst_7_OUT
    );
  reset_II_UIM_3 : X_BUF
    port map (
      I => reset,
      O => reset_II_UIM
    );
  GND_ZERO : X_ZERO
    port map (
      O => GND
    );
  addr_data_0_MC_D1_4 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => addr_data_0_MC_D1
    );
  addr_data_0_MC_D2_PT_0_5 : X_AND2
    port map (
      I0 => addr_data_0_MC_UIM,
      I1 => N_PZ_236,
      O => addr_data_0_MC_D2_PT_0
    );
  addr_data_0_MC_D2_PT_1_6 : X_AND5
    port map (
      I0 => NlwInverterSignal_addr_data_0_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => prs_state_fft2,
      I3 => dataout_en,
      I4 => data_out(0),
      O => addr_data_0_MC_D2_PT_1
    );
  addr_data_0_MC_D2_PT_2_7 : X_AND6
    port map (
      I0 => NlwInverterSignal_addr_data_0_MC_D2_PT_2_IN0,
      I1 => prs_state_fft1,
      I2 => prs_state_fft2,
      I3 => NlwInverterSignal_addr_data_0_MC_D2_PT_2_IN3,
      I4 => data_in_0_MC_UIM,
      I5 => datain_en,
      O => addr_data_0_MC_D2_PT_2
    );
  addr_data_0_MC_D2_PT_3_8 : X_AND8
    port map (
      I0 => NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN0,
      I1 => prs_state_fft1,
      I2 => prs_state_fft2,
      I3 => NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN3,
      I4 => NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN4,
      I5 => ctrl_bits_0_MC_UIM,
      I6 => cntrl_en,
      I7 => NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN7,
      O => addr_data_0_MC_D2_PT_3
    );
  addr_data_0_MC_D2_9 : X_OR4
    port map (
      I0 => addr_data_0_MC_D2_PT_0,
      I1 => addr_data_0_MC_D2_PT_1,
      I2 => addr_data_0_MC_D2_PT_2,
      I3 => addr_data_0_MC_D2_PT_3,
      O => addr_data_0_MC_D2
    );
  addr_data_0_MC_XOR : X_XOR2
    port map (
      I0 => addr_data_0_MC_D1,
      I1 => addr_data_0_MC_D2,
      O => addr_data_0_MC_D
    );
  addr_data_0_MC_UIM_10 : X_BUF
    port map (
      I => addr_data_0_MC_Q_tsim_ireg_Q,
      O => addr_data_0_MC_UIM
    );
  addr_data_0_MC_OE_11 : X_BUF
    port map (
      I => addr_data_0_MC_BUFOE_OUT,
      O => addr_data_0_MC_OE
    );
  FOOBAR1_ctinst_7_12 : X_AND3
    port map (
      I0 => NlwInverterSignal_FOOBAR1_ctinst_7_IN0,
      I1 => prs_state_fft1,
      I2 => prs_state_fft2,
      O => FOOBAR1_ctinst_7
    );
  rd_n_II_UIM_13 : X_BUF
    port map (
      I => rd_n,
      O => rd_n_II_UIM
    );
  prs_state_fft1_14 : X_BUF
    port map (
      I => prs_state_fft1_MC_Q,
      O => prs_state_fft1
    );
  prs_state_fft1_MC_R_OR_PRLD_15 : X_OR2
    port map (
      I0 => FOOBAR3_ctinst_7,
      I1 => PRLD,
      O => prs_state_fft1_MC_R_OR_PRLD
    );
  prs_state_fft1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft1_MC_R_OR_PRLD,
      O => prs_state_fft1_MC_Q
    );
  prs_state_fft1_MC_D1_16 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft1_MC_D1
    );
  prs_state_fft1_MC_D2_PT_0_17 : X_AND3
    port map (
      I0 => prs_state_fft1,
      I1 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN1,
      I2 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN2,
      O => prs_state_fft1_MC_D2_PT_0
    );
  prs_state_fft1_MC_D2_PT_1_18 : X_AND4
    port map (
      I0 => rd_n_II_UIM,
      I1 => prs_state_fft1,
      I2 => prs_state_fft2,