uc_interface_timesim.vhd

8051接口VHDL代码

  signal addr_data_3_MC_D : STD_LOGIC; 
  signal addr_data_3_MC_D1 : STD_LOGIC; 
  signal addr_data_3_MC_UIM : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_3_MC_UIM : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_3 : STD_LOGIC; 
  signal ctrl_bits_3_MC_UIM : STD_LOGIC; 
  signal addr_data_3_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_3_MC_D2 : STD_LOGIC; 
  signal addr_data_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_3_MC_Q : STD_LOGIC; 
  signal data_out_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_3_MC_D : STD_LOGIC; 
  signal data_out_3_MC_D1 : STD_LOGIC; 
  signal app_data_3_II_UIM : STD_LOGIC; 
  signal data_out_3_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_3_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_3_MC_D2 : STD_LOGIC; 
  signal data_in_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_3_MC_Q : STD_LOGIC; 
  signal data_in_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_3_MC_D : STD_LOGIC; 
  signal data_in_3_MC_D1 : STD_LOGIC; 
  signal data_in_3_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_3_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_3_MC_D2 : STD_LOGIC; 
  signal data_in_3_MC_D_TFF : STD_LOGIC; 
  signal status_reg_3_MC_Q : STD_LOGIC; 
  signal status_reg_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal status_reg_3_MC_D : STD_LOGIC; 
  signal data_rdy_II_UIM : STD_LOGIC; 
  signal status_reg_3_MC_D1_PT_0 : STD_LOGIC; 
  signal status_reg_3_MC_D1 : STD_LOGIC; 
  signal status_reg_3_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ctrl_bits_3_MC_Q : STD_LOGIC; 
  signal ctrl_bits_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal ctrl_bits_3_MC_D : STD_LOGIC; 
  signal ctrl_bits_3_MC_D1 : STD_LOGIC; 
  signal ctrl_bits_3_MC_D2_PT_0 : STD_LOGIC; 
  signal ctrl_bits_3_MC_D2_PT_1 : STD_LOGIC; 
  signal ctrl_bits_3_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_3_MC_D_TFF : STD_LOGIC; 
  signal addr_data_4_MC_Q : STD_LOGIC; 
  signal addr_data_4_MC_OE : STD_LOGIC; 
  signal addr_data_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_4_MC_D : STD_LOGIC; 
  signal addr_data_4_MC_D1 : STD_LOGIC; 
  signal addr_data_4_MC_UIM : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_4_MC_UIM : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_3 : STD_LOGIC; 
  signal ctrl_bits_4_MC_UIM : STD_LOGIC; 
  signal addr_data_4_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_4_MC_D2 : STD_LOGIC; 
  signal addr_data_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_4_MC_Q : STD_LOGIC; 
  signal data_out_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_4_MC_D : STD_LOGIC; 
  signal data_out_4_MC_D1 : STD_LOGIC; 
  signal app_data_4_II_UIM : STD_LOGIC; 
  signal data_out_4_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_4_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_4_MC_D2 : STD_LOGIC; 
  signal data_in_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_4_MC_Q : STD_LOGIC; 
  signal data_in_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_4_MC_D : STD_LOGIC; 
  signal data_in_4_MC_D1 : STD_LOGIC; 
  signal data_in_4_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_4_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_4_MC_D2 : STD_LOGIC; 
  signal data_in_4_MC_D_TFF : STD_LOGIC; 
  signal status_reg_4_MC_Q : STD_LOGIC; 
  signal status_reg_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal status_reg_4_MC_D : STD_LOGIC; 
  signal need_data_II_UIM : STD_LOGIC; 
  signal status_reg_4_MC_D1_PT_0 : STD_LOGIC; 
  signal status_reg_4_MC_D1 : STD_LOGIC; 
  signal status_reg_4_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ctrl_bits_4_MC_Q : STD_LOGIC; 
  signal ctrl_bits_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal ctrl_bits_4_MC_D : STD_LOGIC; 
  signal ctrl_bits_4_MC_D1 : STD_LOGIC; 
  signal ctrl_bits_4_MC_D2_PT_0 : STD_LOGIC; 
  signal ctrl_bits_4_MC_D2_PT_1 : STD_LOGIC; 
  signal ctrl_bits_4_MC_D2 : STD_LOGIC; 
  signal ctrl_bits_4_MC_D_TFF : STD_LOGIC; 
  signal addr_data_5_MC_Q : STD_LOGIC; 
  signal addr_data_5_MC_OE : STD_LOGIC; 
  signal addr_data_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_5_MC_D : STD_LOGIC; 
  signal addr_data_5_MC_D1 : STD_LOGIC; 
  signal addr_data_5_MC_UIM : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_5_MC_UIM : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_3 : STD_LOGIC; 
  signal start_MC_UIM : STD_LOGIC; 
  signal addr_data_5_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_5_MC_D2 : STD_LOGIC; 
  signal addr_data_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_5_MC_Q : STD_LOGIC; 
  signal data_out_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_5_MC_D : STD_LOGIC; 
  signal data_out_5_MC_D1 : STD_LOGIC; 
  signal app_data_5_II_UIM : STD_LOGIC; 
  signal data_out_5_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_5_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_5_MC_D2 : STD_LOGIC; 
  signal data_in_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_5_MC_Q : STD_LOGIC; 
  signal data_in_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_5_MC_D : STD_LOGIC; 
  signal data_in_5_MC_D1 : STD_LOGIC; 
  signal data_in_5_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_5_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_5_MC_D2 : STD_LOGIC; 
  signal data_in_5_MC_D_TFF : STD_LOGIC; 
  signal status_reg_5_MC_Q : STD_LOGIC; 
  signal status_reg_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal status_reg_5_MC_D : STD_LOGIC; 
  signal int_n_MC_UIM : STD_LOGIC; 
  signal status_reg_5_MC_D1_PT_0 : STD_LOGIC; 
  signal status_reg_5_MC_D1 : STD_LOGIC; 
  signal status_reg_5_MC_D2 : STD_LOGIC; 
  signal int_n_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal int_n_MC_Q : STD_LOGIC; 
  signal int_n_MC_D : STD_LOGIC; 
  signal FOOBAR4_ctinst_0 : STD_LOGIC; 
  signal int_n_MC_D1 : STD_LOGIC; 
  signal int_reset : STD_LOGIC; 
  signal int_n_MC_D2_PT_0 : STD_LOGIC; 
  signal int_en : STD_LOGIC; 
  signal int_n_MC_D2_PT_1 : STD_LOGIC; 
  signal error_II_UIM : STD_LOGIC; 
  signal int_n_MC_D2_PT_2 : STD_LOGIC; 
  signal int_n_MC_D2_PT_3 : STD_LOGIC; 
  signal int_n_MC_D2 : STD_LOGIC; 
  signal int_reset_MC_Q : STD_LOGIC; 
  signal int_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal int_reset_MC_D : STD_LOGIC; 
  signal int_reset_MC_D1 : STD_LOGIC; 
  signal int_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal int_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal int_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal int_reset_MC_D2 : STD_LOGIC; 
  signal int_en_MC_Q : STD_LOGIC; 
  signal int_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal int_en_MC_D : STD_LOGIC; 
  signal int_en_MC_D1 : STD_LOGIC; 
  signal int_en_MC_D2_PT_0 : STD_LOGIC; 
  signal int_en_MC_D2_PT_1 : STD_LOGIC; 
  signal int_en_MC_D2 : STD_LOGIC; 
  signal int_en_MC_D_TFF : STD_LOGIC; 
  signal start_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal start_MC_Q : STD_LOGIC; 
  signal start_MC_R_OR_PRLD : STD_LOGIC; 
  signal start_MC_D : STD_LOGIC; 
  signal start_MC_D1 : STD_LOGIC; 
  signal start_MC_D2_PT_0 : STD_LOGIC; 
  signal start_MC_D2_PT_1 : STD_LOGIC; 
  signal start_MC_D2 : STD_LOGIC; 
  signal start_MC_D_TFF : STD_LOGIC; 
  signal addr_data_6_MC_Q : STD_LOGIC; 
  signal addr_data_6_MC_OE : STD_LOGIC; 
  signal addr_data_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_6_MC_D : STD_LOGIC; 
  signal addr_data_6_MC_D1 : STD_LOGIC; 
  signal addr_data_6_MC_UIM : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_6_MC_UIM : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_6_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_6_MC_D2 : STD_LOGIC; 
  signal addr_data_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_6_MC_Q : STD_LOGIC; 
  signal data_out_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_6_MC_D : STD_LOGIC; 
  signal data_out_6_MC_D1 : STD_LOGIC; 
  signal app_data_6_II_UIM : STD_LOGIC; 
  signal data_out_6_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_6_MC_D2 : STD_LOGIC; 
  signal data_in_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_6_MC_Q : STD_LOGIC; 
  signal data_in_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_6_MC_D : STD_LOGIC; 
  signal data_in_6_MC_D1 : STD_LOGIC; 
  signal data_in_6_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_6_MC_D2 : STD_LOGIC; 
  signal data_in_6_MC_D_TFF : STD_LOGIC; 
  signal status_reg_6_MC_Q : STD_LOGIC; 
  signal status_reg_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal status_reg_6_MC_D : STD_LOGIC; 
  signal status_reg_6_MC_D1_PT_0 : STD_LOGIC; 
  signal status_reg_6_MC_D1 : STD_LOGIC; 
  signal status_reg_6_MC_D2 : STD_LOGIC; 
  signal addr_data_7_MC_Q : STD_LOGIC; 
  signal addr_data_7_MC_OE : STD_LOGIC; 
  signal addr_data_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal addr_data_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal addr_data_7_MC_D : STD_LOGIC; 
  signal addr_data_7_MC_D1 : STD_LOGIC; 
  signal addr_data_7_MC_UIM : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_0 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_7_MC_UIM : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_2 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_3 : STD_LOGIC; 
  signal addr_data_7_MC_D2_PT_4 : STD_LOGIC; 
  signal addr_data_7_MC_D2 : STD_LOGIC; 
  signal addr_data_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal data_out_7_MC_Q : STD_LOGIC; 
  signal data_out_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_out_7_MC_D : STD_LOGIC; 
  signal data_out_7_MC_D1 : STD_LOGIC; 
  signal app_data_7_II_UIM : STD_LOGIC; 
  signal data_out_7_MC_D2_PT_0 : STD_LOGIC; 
  signal data_out_7_MC_D2_PT_1 : STD_LOGIC; 
  signal data_out_7_MC_D2 : STD_LOGIC; 
  signal data_in_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_in_7_MC_Q : STD_LOGIC; 
  signal data_in_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_in_7_MC_D : STD_LOGIC; 
  signal data_in_7_MC_D1 : STD_LOGIC; 
  signal data_in_7_MC_D2_PT_0 : STD_LOGIC; 
  signal data_in_7_MC_D2_PT_1 : STD_LOGIC; 
  signal data_in_7_MC_D2 : STD_LOGIC; 
  signal data_in_7_MC_D_TFF : STD_LOGIC; 
  signal status_reg_7_MC_Q : STD_LOGIC; 
  signal status_reg_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal status_reg_7_MC_D : STD_LOGIC; 
  signal done_II_UIM : STD_LOGIC; 
  signal status_reg_7_MC_D1_PT_0 : STD_LOGIC; 
  signal status_reg_7_MC_D1 : STD_LOGIC; 
  signal status_reg_7_MC_D2 : STD_LOGIC; 
  signal data_rdy_reset_MC_Q : STD_LOGIC; 
  signal data_rdy_reset_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_rdy_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_rdy_reset_MC_D : STD_LOGIC; 
  signal data_rdy_reset_MC_D1 : STD_LOGIC; 
  signal data_rdy_reset_MC_UIM : STD_LOGIC; 
  signal data_rdy_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal data_rdy_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal data_rdy_reset_MC_D2 : STD_LOGIC; 
  signal error_reset_MC_Q : STD_LOGIC; 
  signal error_reset_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal error_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal error_reset_MC_D : STD_LOGIC; 
  signal error_reset_MC_D1 : STD_LOGIC; 
  signal error_reset_MC_UIM : STD_LOGIC; 
  signal error_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal error_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal error_reset_MC_D2_PT_2 : STD_LOGIC; 
  signal error_reset_MC_D2 : STD_LOGIC; 
  signal need_data_reset_MC_Q : STD_LOGIC; 
  signal need_data_reset_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal need_data_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal need_data_reset_MC_D : STD_LOGIC; 
  signal need_data_reset_MC_D1 : STD_LOGIC; 
  signal need_data_reset_MC_UIM : STD_LOGIC; 
  signal need_data_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal need_data_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal need_data_reset_MC_D2 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_7_OUT : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_data_0_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_fft2_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_addr_match_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_236_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_dataout_en_MC_D1_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_datain_en_MC_D1_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_cntrl_en_MC_D1_PT_0_IN12 : STD_LOGIC;