uc_interface_tb.vhd

8051接口VHDL代码

        wait until clk'event and clk = '1';
        wait until clk'event and clk = '1';
        reset <= not(RESET_ACTIVE);

        -- run a uC bus cycle with PSEN_N asserted to insure that these
        -- bus cycles are ignored
        assert_psen <= '1';
        write <= '0';
        uc_addr <= BASE_ADDR & CTRL_ADDR;
        uc_data <= FA;
        go <= '1';
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '1';
        go <= '0';
        wait until uc_done = '1';
        assert_psen <= '0';
        
        -- run a uC bus cycle with the wrong address to insure that these
        -- bus cycles are ignored
        write <= '1';
        uc_addr <= BASE_ADDR & DE;
        uc_data <= FA;
        go <= '1';
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '1';
        go <= '0';
        wait until uc_done = '1';
        
        -- Before starting the test, read the status register 
        -- to insure that the bus is not busy 
        write <= '0';
        uc_addr <= BASE_ADDR & STATUS_ADDR;
        go <= '1';
        wait until clk'event and clk ='1';
        wait until clk'event and clk ='1';
        go <= '0';
        wait until uc_done = '1';
                                    
        -- continue reading status register until bus busy negates
        while ucdata_in(DONE_BIT) = '1' loop
            write <= '0';
            uc_addr <= BASE_ADDR & STATUS_ADDR;
            go <= '1';
            wait until clk'event and clk='1';
            wait until clk'event and clk='1';
            go <= '0';
            wait until uc_done = '1';
        end loop;

        -- bus is no longer busy, prepare to start test
        -- enable application logic and interrupts
        en_app <= '1';
        en_int <= '1';
            
        -- wait for a clock signal to allow signal assignments to 
        -- take effect
        wait until clk'event and clk = '1';
                
        -- Now need to call the state machine to write registers
        -- to configure the application logic, then need to generate the START signal
  
        -- Variable K will loop through the register writes to set up the 
        -- control registers,write the first input data word, 
        -- and assert the START  signal
                write <= '1';
                for k in 0 to 2 loop
                    -- first setup data and address
                    case k is
                        when 0 =>
                            -- write to control register
                            uc_addr <= BASE_ADDR & CTRL_ADDR;  
                            -- first set APP_EN, EN_INT, and other ctrl bits
                            -- without generating START
                            uc_data <= en_app & en_int & '0' & "00000";
                        when 1 =>
                            -- now write first data to be transmitted
                            uc_addr <= BASE_ADDR & DATAIN_ADDR;
                            uc_data <= TST_DATA_OUT(0);
                        when 2 =>
                            -- now set start in the control register
                            uc_addr <= BASE_ADDR & CTRL_ADDR;
                            uc_data <= en_app & en_int & '1' & "00000";
                        when others =>
                            uc_addr <= (others => '0');
                            uc_data <= (others => '0');
                    end case;
                
                    -- wait a clock signal for signal assignments to take affect
                    wait until clk'event and clk = '1';
                    
                    -- now signal uC state machine to write to SPI interface
                    go <= '1';
                    wait until clk'event and clk = '1';
                    wait until clk'event and clk = '1';
                    go <= '0';
                    wait until uc_done = '1';
                end loop;

                for k in 0 to NUM_DATA_WORDS-1 loop
                    -- loop for number of data words to input to application logic

                    -- wait for INT_N from the application logic 
                    if int_n = '1' then
                        -- wait for interrupt
                        wait until int_n = '0'; 
                    end if; 
            
                    -- interrupt has occurred, read status register
                    -- to determine cause of interrupt
                    uc_addr <= BASE_ADDR & STATUS_ADDR;
                    write <= '0';
                    go <= '1';
                    wait until clk'event and clk ='1';
                    wait until clk'event and clk = '1';
                    go <= '0';
                    wait until uc_done = '1';
            
                    -- Determine cause of interrupt
                    -- if ERROR is asserted, write a '0' to the bit to clear it
                    -- wait for this bit to clear (meaning that error went away)
                    -- then reset the application logic
                    if ucdata_in (ERROR_BIT) = '1' then
                        while ucdata_in(ERROR_BIT) = '1' loop
                            -- ERROR - 
                            -- reset this bit and the interrupt  by writing a '0' to
                            -- this bit in the status register
                            uc_addr <= BASE_ADDR & STATUS_ADDR;
                            uc_data <= (others => '0');
    
                            write <= '1';
                            go <= '1';
                            wait until clk'event and clk = '1';
                            wait until clk'event and clk = '1';
                            go <= '0';
                            wait until uc_done = '1';
        
                        
                            -- now read status register again to see if 
                            -- ERROR has gone away
                            uc_addr <= BASE_ADDR & STATUS_ADDR;
                            write <= '0';
                            go <= '1';
                            wait until clk'event and clk ='1';
                            wait until clk'event and clk = '1';
                            go <= '0';
                            wait until uc_done = '1';
                         end loop;
                        
                        
                        -- now reset logic by negating APP_EN in 
                        -- control register
                        uc_addr <= BASE_ADDR & CTRL_ADDR;
                        uc_data <= '0' & en_int & '1' & "00000";
                        write <= '1';
                        go <= '1';
                        wait until clk'event and clk = '1';
                        wait until clk'event and clk = '1';
                        go <= '0';
                        wait until uc_done = '1';
                        
                        
                        -- set signal that will exit loop
                        exit_loop <= '1';
                        
                    else 
                        -- no error
                        exit_loop <= '0';
                        if ucdata_in(NEEDDATA_BIT) = '1' then
                            -- NEED_DATA flag asserted
                            -- write new input data
                            -- unless last data has already been written
                            -- if last data has been written, write to control register
                            -- to negate start
            
                            if k = NUM_DATA_WORDS-1 then
                                -- all data words have been written to the input data register,
                                -- write to control register to negate start
                                uc_addr <= BASE_ADDR & CTRL_ADDR;
                                uc_data <= en_app & en_int & '0' & "00000";
                            else
                                -- write next data word to be transmitted
                                -- to input data register
                                uc_addr <= BASE_ADDR & DATAIN_ADDR;
                                uc_data <= TST_DATA_OUT(k+1);
                            end if;
                        
                            write <= '1';
                            go <= '1';
                            wait until clk'event and clk = '1';
                            wait until clk'event and clk = '1';
                            go <= '0';
                            wait until uc_done = '1';
                        end if;
            
                        -- if DATA_RDY flag is asserted, then read output data register
                        if ucdata_in(DATARDY_BIT) = '1' then
                            
                                -- read output data register 
                                uc_addr <= BASE_ADDR & DATAOUT_ADDR;
                                write <= '0';
                                go <= '1';
                                wait until clk'event and clk = '1';
                                wait until clk'event and clk = '1';
                                go <= '0';
                                wait until uc_done = '1';
                                
                                -- first time through loop, there should be no DATA_RDY flag
                                -- therefore, compare received data with expected data
                                -- using loop index -1
                                if ucdata_in = EXPECTED_DATA(k-1) then
                                    data_error <= '0';
                                else
                                    data_error <= '1';
                                end if;
                            
                        end if; 
                    end if;
                   
                   -- write '0' to the int_n bit in the status register to clear it.
                   uc_addr <= BASE_ADDR & STATUS_ADDR;
                   uc_data <= (others => '0');
                   write <= '1';
                   go <= '1';
                   wait until clk'event and clk = '1';
                   wait until clk'event and clk = '1';
                   go <= '0';
                   wait until uc_done = '1';

                end loop;

                if exit_loop = '0' then
                    if int_n = '1'  then
                        -- wait for interrupt indicating that the last data word
                        -- is ready
                        wait until int_n = '0'; 
                    end if; 

                    -- read the output data register 
                    write <= '0';
                    uc_addr <= BASE_ADDR & DATAOUT_ADDR;
                    go <= '1';
                    wait until clk'event and clk = '1';
                    wait until clk'event and clk = '1';
                    go <= '0';
                    wait until uc_done = '1';
                   
                   if ucdata_in = EXPECTED_DATA(NUM_DATA_WORDS-1) then
                        data_error <= '0';
                   else
                        data_error <= '1';
                   end if;

                end if;
                
                -- write to control register to reset application logic, i.e.
                -- negate APP_EN
                uc_addr <= BASE_ADDR & CTRL_ADDR;
                uc_data <= (others => '0');
                write <= '1';
                go <= '1';
                wait until clk'event and clk = '1';
                wait until clk'event and clk = '1';
                go <= '0';
               wait until uc_done = '1';

                
wait;

end process;