uc_interface_tb.vhd

8051接口VHDL代码

-- uc_interface_tb.vhd
--
-- Created: 11/05/00 ALS
--      This file provides an 8051 uC model based on timing parameters from 8051 data sheet.
--
--
-- **************************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

-- ************************************* Constant Declarations **************************
constant RESET_ACTIVE   : STD_LOGIC := '0';
constant CLK_PERIOD     : time := 50 nS;        -- system clock period


-- 8051 Timing constants
-- The constant TCLCL should be set to match the actual clock period of the 8051
-- The equations for the other constants to be modified to match the data sheet of the 
-- 8051 uC used in the design

constant TCLCL      : time := 62500 pS;         -- 8051 clock period - 16MHz
constant TLHLL      : time := 2*TCLCL - 40 nS;  -- ALE negated pulse width
constant TAVLL      : time := TCLCL - 50 nS;    -- Address valid to ALE low
constant TLLAX      : time := TCLCL - 35 nS;    -- Address low after ALE low
constant TQVWX      : time := TCLCL - 60 nS;    -- Data valid to WR_N transition
constant TWLWH      : time := 6*TCLCL - 100 nS; -- WR_N pulse width
constant TWHQX      : time := TCLCL - 50 nS;    -- Data hold after WR_N negation
constant TWHLH      : time := TCLCL - 40 nS;    -- WR_N or RD_N negation to ALE_N negation
constant TRLAZ      : time := 0 nS;             -- RD_N assertion to address float
constant TRLDV      : time := 5*TCLCL - 165 nS; -- RD_N assertion to valid data in
constant TRLRH      : time := 6*TCLCL - 100 nS; -- RD_N pulse width
constant TLLPL      : time := TCLCL - 40 nS;    -- ALE_N assertion to PSEN_N assertion
constant TPLAZ      : time := 10 nS;            -- PSEN_N assertion to address float
constant TPLIV      : time := 3*TCLCL - 115 nS; -- PSEN_N assertion to instruction valid
constant TPLPH      : time := 3*TCLCL - 45 nS;  -- PSEN_N pulse width
 
-- the constant below is used to assert ERROR. If set to 0, ERROR will never assert.
-- if non-zero, ERROR will assert this time period after beginning of simulation, stay
-- asserted for this time period, and then negate. 
-- Note that setting this constant and running a test of ERROR will probably cause the 
-- data read in from the SPIRR not to match the expected value, thus DATA_ERROR may assert for
-- a data period
constant ERROR_ASSERT_TIME  : time  := 0 uS;

-- the constants below are used to model the system clock cycles needed by the application logic to
-- grab the first data word from the input data register and the number of clock cycles needed
-- by the application logic to "work" on the data 
-- the signal CLK_CNT is used to count the clock
constant APP_FIRST_WORD_ACCESS  : integer    := 3;
constant APP_WORK_DATA_CLKS     : integer    := 40;

-- register addresses
-- Set the number of address bits representing the device address
constant DEVICE_ADDR_BITS   : integer       :=  8;    -- default is 8

-- Set the number of address bits representing the register addresses
constant REG_ADDR_BITS      : integer       :=  8;    -- default is 8

-- Set the base address for CoolRunner CPLD 
constant BASE_ADDR  : STD_LOGIC_VECTOR(DEVICE_ADDR_BITS-1 downto 0) := "00000000";

-- Set the Register Addresses (4 Total):
-- Status Register (BASE + 80h)
constant STATUS_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000000";

-- Control Register (BASE + 82h)
constant CTRL_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000010";

-- Input Data Register (BASE + 84h)
constant DATAIN_ADDR    : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000100";

-- Output Data Register (BASE + 86h)
constant DATAOUT_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000110";

-- number of data words and data words
constant NUM_DATA_WORDS : integer   := 4;
constant ALL_ONES   : std_logic_vector(7 downto 0) := "11111111";
constant ALL_ZEROS  : std_logic_vector(7 downto 0) := "00000000";
constant DE         : std_logic_vector(7 downto 0) := "11011110";
constant AD         : std_logic_vector(7 downto 0) := "10101101";
constant BE         : std_logic_vector(7 downto 0) := "10111110";
constant EF         : std_logic_vector(7 downto 0) := "11101111";
constant FA         : std_logic_vector(7 downto 0) := "11111010";
constant CE         : std_logic_vector(7 downto 0) := "11001110";

-- bit locations in status register
constant DONE_BIT       : integer   := 7;           -- DONE is bit 7 in Status Register
constant ERROR_BIT      : integer   := 6;           -- ERROR is bit 6 in Status Register
constant NEEDDATA_BIT   : integer   := 4;           -- NEED_DATA is bit 4 in Status Register
constant DATARDY_BIT    : integer   := 3;           -- DATA_RDY is bit 3 in Status Register


-- test data
type TEST_DATA is array (0 to NUM_DATA_WORDS-1) of std_logic_vector (7 downto 0);

-- assign data to be input to application logic in this array
constant TST_DATA_OUT : TEST_DATA := (
                        (DE),       -- write first word to be input to application logic
                        (AD),       -- next data word 
                        (BE),       -- next data word 
                        (EF)        -- last data word 
                        );

-- assign expected data output from application logic in this array
constant EXPECTED_DATA : TEST_DATA := (
                        (DE),       -- write first word to be output from application logic
                        (AD),       -- next data word 
                        (BE),       -- next data word 
                        (EF)        -- last data word 
                        );

--*************************************** Component Declaration *****************************
-- 
    component uc_interface
    port(
        clk             : in std_logic;
        reset           : in std_logic;
        addr            : in std_logic_vector(7 downto 0);
        ale_n           : in std_logic;
        psen_n          : in std_logic;
        rd_n            : in std_logic;
        wr_n            : in std_logic;
        done            : in std_logic;
        error           : in std_logic;
        need_data       : in std_logic;
        data_rdy        : in std_logic;
        data_rdy_reset  : out std_logic;
        dataout_load    : in std_logic;
        app_data        : in std_logic_vector(7 downto 0);    
        addr_data       : inout std_logic_vector(7 downto 0);
        int_n           : inout std_logic;
        app_en          : inout std_logic;
        start           : inout std_logic;      
        ctrl_bits       : inout std_logic_vector(4 downto 0);
        error_reset     : out std_logic;
        need_data_reset : out std_logic;
        data_in         : inout std_logic_vector(7 downto 0)
        );
    end component;
    
    
    
-- ************************************** Signal Declarations *******************************
-- uC bus signals
signal addr             :  std_logic_vector(7 downto 0);
signal addr_data        :  std_logic_vector(7 downto 0);
signal ale_n            :  std_logic;
signal psen_n           :  std_logic;
signal rd_n             :  std_logic;
signal wr_n             :  std_logic;
signal int_n            :  std_logic;

-- reset and clock
signal reset            :  std_logic;
signal clk              :  std_logic;

-- signals needed to interface to CoolRunner CPLD
signal app_en, en_app   :  std_logic;       -- app_en is from uC interface to application logic
                                            -- en_app is internal testbench signal
signal en_int           :  std_logic;       -- en_int is internal testbench signal
signal start            :  std_logic;
signal ctrl_bits        :  std_logic_vector(4 downto 0);
signal done             :  std_logic;
signal error            :  std_logic;
signal need_data        :  std_logic;
signal data_rdy         :  std_logic;
signal error_reset      :  std_logic;
signal need_data_reset  :  std_logic;
signal data_rdy_reset   :  std_logic;
signal dataout_load     :  std_logic;
signal app_data         :  std_logic_vector(7 downto 0);
signal data_in          :  std_logic_vector(7 downto 0);


-- testbench signals
signal ad_out,ucdata_in : std_logic_vector(7 downto 0);
signal ucdata_in_ce     : std_logic;    -- clock enable for input data register
signal write            : std_logic;    -- indicates a write cycle
signal assert_psen      : std_logic;    -- indicates a program store cycle
signal go, uc_done      : std_logic;    -- handshake signals to  state machine
signal ad_oe            : std_logic;    -- address/data bus output enable
signal uc_addr          : std_logic_vector(15 downto 0);-- addr to be output by uC 
signal uc_data          : std_logic_vector(7 downto 0); -- data to be output by uC
signal data_error       : std_logic;    -- indicates that data received <> data transmitted
signal exit_loop        : std_logic;    -- indicates that SPIERR was asserted
signal clk_cnt          : integer;      -- counts clks for APP_FIRST_WORD_ACCESS
                                        -- and for APP_WORK_DATA_CLKS
signal first_loop       : std_logic := '1';


BEGIN

-- ************************************ UUT Instantiation ********************************

UUT: uc_interface 
    port map(
        clk                 => clk,
        reset               => reset,
        addr_data           => addr_data,
        addr                => addr,
        ale_n               => ale_n,
        psen_n              => psen_n,
        rd_n                => rd_n,
        wr_n                => wr_n,
        int_n               => int_n,
        app_en              => app_en,
        start               => start,
        ctrl_bits           => ctrl_bits,
        done                => done,
        error               => error,
        need_data           => need_data,
        data_rdy            => data_rdy,
        error_reset         => error_reset,
        need_data_reset     => need_data_reset,
        data_rdy_reset      => data_rdy_reset,
        dataout_load        => dataout_load,
        app_data            => app_data,
        data_in             => data_in
    );


-- ************************************* Test Bench Processes and Code **************************

   -- Define the bi-directional data bus 
   -- use pulldowns when tri-stated
   addr_data <= ad_out when ad_oe = '1' 
        else (others => 'L');


-- ************************************ Clock Process *************************************
-- Process:  CREATE_CLK
-- Function:  Create 20Mhz clock
CREATE_CLK: process
    begin
        clk <= '0';
        wait for CLK_PERIOD/2;
        clk <= '1';
        wait for CLK_PERIOD/2;

    end process;


-- *********************************** Main Control Process *********************************
-- define the main controlling process that triggers the state machines
MAIN : process
   
   variable i,j,k   : integer := 0;     -- loop counters

   begin
        -- initialize control signals
        uc_addr <= (others => '0');
        uc_data <= (others => '0');
        go <= '0';
        write <= '0';
        assert_psen <= '0';
        data_error <= '0';
        en_app <= '0';
        en_int <= '0';
        exit_loop <= '0';

        -- assert RESET for two clocks
        reset <= RESET_ACTIVE;