uc_interface.vhd

8051接口VHDL代码

-- *****************************************************************************
-- uc_interface.vhd
-- 
-- Created:  11/4/00 ALS
--      This file provides an 8051 external data memory bus interface 
--      for CoolRunner CPLDs. This file contains the state machine to 
--      interface on the 8051 bus as well as the address registers, the address
--      decode logic, and example control registers, status registers, data input
--      registers, and data output registers. Interrupt logic is also included.
--
--      Note that this code should be modified to meet the requirements of the
--      system.
--
--
-- *****************************************************************************

library IEEE;
use IEEE.std_logic_1164.all;


entity uC_interface is
    port(
            -- 8051  bus interface
            clk         : in  std_logic;
            reset       : in  std_logic;     
        
            addr_data   : inout std_logic_vector (7 downto 0);  -- multiplexed address/data bus
            addr        : in    std_logic_vector (7 downto 0);  -- high byte of address 
            ale_n       : in    std_logic;                      -- address latch enable, active low 
            psen_n      : in    std_logic;                      -- program store enable, active low
        
            -- directional pins
            rd_n        : in    std_logic;  -- active low read strobe 
            wr_n        : in    std_logic;  -- active low write strobe
            int_n       : inout std_logic;  -- active low interrupt request
    
            -- interface to application logic
            -- control signals from control register
            app_en      : inout std_logic;                      -- enables the application logic
            start       : inout std_logic;                      -- start operation
            ctrl_bits   : inout std_logic_vector(4 downto 0);   -- user definable control bits
            
            -- status register signals from application logic
            done        : in    std_logic;  -- operation is complete
            error       : in    std_logic;  -- error in application logic
            need_data   : in    std_logic;  -- flag indicating that data input register is empty
            data_rdy    : in    std_logic;  -- flag indicating that data output register has data
            
            -- resets for status flags
            error_reset     : out   std_logic;  -- error flag is reset whenever a 0 is written 
                                                -- to this bit in status register
            
            need_data_reset : out std_logic;    -- need_data flag reset when data input register 
                                                -- is written
            data_rdy_reset  : out    std_logic;  -- data_rdy flag reset when data output register
                                                -- is read
            
            -- output data register signals
            dataout_load    : in    std_logic;  -- load control signal to data output register
            app_data        : in    std_logic_vector(7 downto 0);  -- data to load into data output register
            
            -- input data register which provides data to application logic
            data_in         : inout std_logic_vector(7 downto 0)
        
        );
        

end uC_interface;




architecture BEHAVIOUR of uC_interface is

--**************************** Constants ***************************************
-- Set the active reset level
constant RESET_ACTIVE : STD_LOGIC := '0';           -- default is active low reset
        
-- Set the number of address bits representing the device address
constant DEVICE_ADDR_BITS   : integer       :=  8;    -- default is 8

-- Set the number of address bits representing the register addresses
constant REG_ADDR_BITS      : integer       :=  8;    -- default is 8

-- Set the base address for CoolRunner CPLD 
constant BASE_ADDR  : STD_LOGIC_VECTOR(DEVICE_ADDR_BITS-1 downto 0) := "00000000";

-- Set the Register Addresses (4 Total):
-- Status Register (BASE + 80h)
constant STATUS_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000000";

-- Control Register (BASE + 82h)
constant CTRL_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000010";

-- Input Data Register (BASE + 84h)
constant DATAIN_ADDR    : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000100";

-- Output Data Register (BASE + 86h)
constant DATAOUT_ADDR     : STD_LOGIC_VECTOR(REG_ADDR_BITS-1 downto 0) := "10000110";

--**************************** Signal Definitions ***************************************

-- uc data bus signals
signal uc_data_out  : std_logic_vector(7 downto 0); -- data to be output to 8051 
signal uc_data_in   : std_logic_vector(7 downto 0); -- data input from the 8051
signal uc_data_oe   : std_logic;                    -- output enable for 8051 data bus

-- State signals for uc interface state machine
type STATE_TYPE is (IDLE, ADDR_DECODE, DATA_TRS, END_CYCLE);
signal prs_state, next_state : STATE_TYPE;                  

-- Address match
signal addr_match    : std_logic;

-- low byte address lines
signal address_low  : std_logic_vector(7 downto 0);

-- entire address - upper byte and lower byte 
signal address      : std_logic_vector(15 downto 0);

-- data registers
signal data_out     : std_logic_vector(7 downto 0); -- output data register

-- status register
signal status_reg   : std_logic_vector(7 downto 0); -- status register

-- Register Enable Lines
signal cntrl_en     : std_logic;        -- control register is addressed
signal stat_en      : std_logic;        -- status register is addressed
signal datain_en    : std_logic;        -- data input register is addressed  
signal dataout_en   : std_logic;        -- data output register is addressed

-- Register reset lines
signal int_reset    : std_logic;    -- writing 0 this bit in the status register 
                                    -- generates a reset to the bit
                                    
-- control register signals that aren't output to application logic
signal int_en        : std_logic;    -- interrupt enable


begin

--************************** Bi-directional 8051 Data Bus **********************************

addr_data   <= uc_data_out when (uc_data_oe = '1') else (others => 'Z');
uc_data_in  <= addr_data when wr_n = '0' else (others => '0');

--************************** uC Interface State Machine *******************************
-- Register process registers next state signals
-- Return to IDLE state whenever RESET is asserted  

UC_SM_REGS: process (clk, reset)
begin
        if reset = RESET_ACTIVE then
            prs_state <= IDLE;
            
        elsif clk'event and clk = '1' then
            prs_state <= next_state;
            
        end if;
    
end process;

-- Combinatorial process determines next state logic
COMBINATIONAL: process (prs_state, ale_n, rd_n, wr_n, addr_match)
    
begin
    
next_state <= prs_state;
uc_data_oe <= '0';
    
    
    case prs_state is
    
        --****************** IDLE State  *********************
        when IDLE =>

                -- Wait for falling edge of ALE_N with PSEN_N negated
            if ale_n = '0' and psen_n = '1' then
                -- falling edge of ALE_N
                next_state <= ADDR_DECODE;
            end if;

        
        --****************** ADDR_DECODE State  *****************
        when ADDR_DECODE =>
            
            -- Check that this module is being address
            if addr_match = '1' then
                    -- Wait for rd_n or wr_n to be asserted
                    if rd_n = '0' or wr_n = '0' then
                        next_state <= DATA_TRS;
                end if;
            else
                -- this module is not being addressed
                  next_state <= IDLE;
            end if;
    
            
        --****************** DATA_TRS State  *********************
        when DATA_TRS =>

                -- Read or write from enabled register (see uC_regs process)
                -- if read cycle, assert the data output enable
                if rd_n = '0' then
                    uc_data_oe <= '1';
                end if;
                
                -- wait until rd_n and wr_n negates before ending cycle
                if rd_n = '1' and wr_n = '1' then
                    next_state <= END_CYCLE;
                end if;

                        
        --****************** END_CYCLE State ********************
        when END_CYCLE =>
                
            
            -- Wait for negation of ale_n
            if (ale_n = '1') then
              next_state <= IDLE;
            end if;
        
             end case;
        
end process;

--************************** Address Registers **********************************
-- This process registers the low byte of address from the multiplexed address/data bus
-- on the falling edge of ale

address_regs: process(reset, ale_n)
begin
        if reset = RESET_ACTIVE then
        
            address_low <= (others => '0');
            
        elsif ale_n'event and ale_n = '0' then
            
            address_low <= addr_data;
        
        end if;
    
end process;

-- the entire address contains the upper and lower address bytes
address <= addr & address_low;

--************************** Address Decode **********************************
-- This process decodes the address and sets enables for the registers
address_decode: process (reset, clk)
begin
    if reset = RESET_ACTIVE then
        
        addr_match   <= '0'; -- signal indicating that base address matches
        
        datain_en   <= '0'; -- input data register enable
        dataout_en  <= '0'; -- output data register enable