pwm.txt

实现三相pwm控制

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


entity comparator_8_bit_e is
	port(clk:in std_logic;
	     va,vb,vc:in std_logic_vector(7 downto 0);
	     pwm_a_on,pwm_a_off,pwm_b_on,pwm_b_off,
             pwm_c_on,pwm_c_off:out std_logic);
end comparator_8_bit_e;


architecture rtl of comparator_8_bit_e is
signal cnt:std_logic_vector(7 downto 0);
SIGNAL CNTB:INTEGER RANGE 0 to 511:=0;
SIGNAL A:INTEGER RANGE -128 to 127:=0;
begin
	
	process(clk)
	begin
		if(clk'event and clk='1') then
		CASE CNTB IS
			WHEN 0 TO 126 =>
				CNTB<=CNTB+1;
				A<=A+1;
			WHEN 127 =>
				CNTB<=CNTB+1;
				A<=127;
			WHEN 128 TO 381 =>
				CNTB<=CNTB+1;
				A<=A-1;
			WHEN 383 =>
				CNTB<=CNTB+1;
				A<=-128;
			WHEN 384 TO 511 =>
				CNTB<=CNTB+1;
				A<=A+1;
			WHEN OTHERS=>
				CNTB<=0;
				A<=0;
		END CASE;
		end if;
	end process;
		cnt<=conv_std_logic_vector(A,8);
	

	process(cnt,va)
	begin
		if va>=cnt then
			pwm_a_on<='1';
			pwm_a_off<='0';
		elsif va<cnt then
			pwm_a_on<='0';
			pwm_a_off<='1';
		else
			pwm_a_on<='0';
			pwm_a_off<='0';
		end if;
	end process;
	
	
	process(cnt,vb)
	begin
		if vb>=cnt then
			pwm_b_on <='1';
			pwm_b_off <='0';
		elsif vb<cnt then 
			pwm_b_on <='0';
			pwm_b_off <='1';
		else
			pwm_b_on <='0';
			pwm_b_off <='0';
		end if;
	end process;


	process(cnt,vc)
	begin
		if vc>=cnt then
			pwm_c_on <='1';
			pwm_c_off <='0';
		elsif vc<cnt then
			pwm_c_on <='0';
			pwm_c_off <='1';
		else 
			pwm_c_on <='0';
			pwm_c_off <='0';
		end if;
	end process;
end rtl;