str73x.s

str73系列 三洋LC75010 控制代码

FIQHandler      B       FIQHandler

PRCCUCMU_Addr   DCD     0                   ; Dummy reference for library

                ELSE

                ; Peripherals IRQ Handlers Address Table
PRCCUCMU_Addr   DCD     PRCCUCMUIRQHandler
EXTIT01_Addr    DCD     EXTIT01IRQHandler
EXTIT02_Addr    DCD     EXTIT02IRQHandler
EXTIT03_Addr    DCD     EXTIT03IRQHandler
EXTIT04_Addr    DCD     EXTIT04IRQHandler
EXTIT05_Addr    DCD     EXTIT05IRQHandler
EXTIT06_Addr    DCD     EXTIT06IRQHandler
EXTIT07_Addr    DCD     EXTIT07IRQHandler
EXTIT08_Addr    DCD     EXTIT08IRQHandler
EXTIT09_Addr    DCD     EXTIT09IRQHandler
EXTIT10_Addr    DCD     EXTIT10IRQHandler
EXTIT11_Addr    DCD     EXTIT11IRQHandler
EXTIT12_Addr    DCD     EXTIT12IRQHandler
EXTIT13_Addr    DCD     EXTIT13IRQHandler
EXTIT14_Addr    DCD     EXTIT14IRQHandler
EXTIT15_Addr    DCD     EXTIT15IRQHandler
DMATRERR_Addr   DCD     DMATRERRIRQHandler
TIM1_Addr       DCD     TIM1IRQHandler
TIM2_Addr       DCD     TIM2IRQHandler
TIM3_Addr       DCD     TIM3IRQHandler
TIM4_Addr       DCD     TIM4IRQHandler
TB0_Addr        DCD     TB0IRQHandler
TB1_Addr        DCD     TB1IRQHandler
TB2_Addr        DCD     TB2IRQHandler
TIM5_Addr       DCD     TIM5IRQHandler
TIM6_Addr       DCD     TIM6IRQHandler
TIM7_Addr       DCD     TIM7IRQHandler
TIM8_Addr       DCD     TIM8IRQHandler
TIM9_Addr       DCD     TIM9IRQHandler
                DCD     0                   ; Reserved
                DCD     0                   ; Reserved
UART2_Addr      DCD     UART2IRQHandler
UART3_Addr      DCD     UART3IRQHandler
FlashEOP_Addr   DCD     FLASHEOPIRQHandler
PWM0_Addr       DCD     PWM0IRQHandler
PWM1_Addr       DCD     PWM1IRQHandler
PWM2_Addr       DCD     PWM2IRQHandler
PWM3_Addr       DCD     PWM3IRQHandler
PWM4_Addr       DCD     PWM4IRQHandler
PWM5_Addr       DCD     PWM5IRQHandler
WIUI_Addr       DCD     WIUIRQHandler
WDGWUT_Addr     DCD     WDGWUTIRQHandler
BSPI0_Addr      DCD     BSPI0IRQHandler
BSPI1_Addr      DCD     BSPI1IRQHandler
BSPI2_Addr      DCD     BSPI2IRQHandler
UART0_Addr      DCD     UART0IRQHandler
UART1_Addr      DCD     UART1IRQHandler
I2C0ITERR_Addr  DCD     I2C0ITERRIRQHandler
I2C1ITERR_Addr  DCD     I2C1ITERRIRQHandler
                DCD     0                   ; Reserved
                DCD     0                   ; Reserved
I2C0ITDDC_Addr  DCD     I2C0ITDDCIRQHandler
I2C1ITDDC_Addr  DCD     I2C1ITDDCIRQHandler
                DCD     0                   ; Reserved
                DCD     0                   ; Reserved
CAN0_Addr       DCD     CAN0IRQHandler
CAN1_Addr       DCD     CAN1IRQHandler
CAN2_Addr       DCD     CAN2IRQHandler
DMA0_Addr       DCD     DMA0IRQHandler
DMA1_Addr       DCD     DMA1IRQHandler
DMA2_Addr       DCD     DMA2IRQHandler
DMA3_Addr       DCD     DMA3IRQHandler
ADC_Addr        DCD     ADCIRQHandler
RTC_Addr        DCD     RTCIRQHandler

                ENDIF
                
                EXPORT  PRCCUCMU_Addr


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   
                NOP     ; Wait for OSC stabilization
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP


; Memory Remapping
                IF      :DEF:REMAP
                LDR     R1, =CFG_BASE
                LDR     R0, [R1, #CFG_R0_OFS]
                ORR     R0, R0, #1
                STR     R0, [R1, #CFG_R0_OFS]
                ENDIF


; Reset Peripherals (except RAM)
                IF      PERIPH_RESET <> 0
                LDR     R0, =CFG_BASE
                LDR     R1, =CFG_PCGR0_Rst
                STR     R1, [R0, #CFG_PCGR0_OFS]
                LDR     R1, =CFG_PCGR1_Rst
                STR     R1, [R0, #CFG_PCGR1_OFS]
                ENDIF


; Setup Enhanced Interrupt Controller
                IF      EIC_SETUP <> 0

                LDR     R0, =CFG_BASE       ; Enable the EIC clock
                LDR     R1, [R0, #CFG_PCGR0_OFS]
                ORR     R1, R1, #0x20000000
                STR     R1, [R0, #CFG_PCGR0_OFS]

                NOP                         ; Wait for EIC stabilization
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP

                LDR     R0, =EIC_BASE
                LDR     R1, =0xE59F0000     ; LDR PC,[PC,#ofs] (High 16-bits)
                STR     R1, [R0, #IVR_OFS]  ; Store into IVR[31:16]
                LDR     R1, =PRCCUCMU_Addr  ; IRQ Address Table
                LDR     R2, =0x0FFF         ; Offset Mask
                AND     R1, R1, R2          ; Mask Offset
                LDR     R2, =0xF3E0         ; Jump Offset = 0x03E0
                                            ; 0xFXXX is used to complete the
                                            ; LDR PC,[PC,#ofs]
                                            ; 0x03E0 = 0x03E8 - 8 (Prefetch)
                                            ; 0 = IVR Address + 0x3E8
                ADD     R1, R1, R2          ; Add Jump Offset
                MOV     R2, #64             ; Number of Channels
                MOV     R3, #SIR0_OFS       ; Offset to SIR0
EIC_Loop        MOV     R4, R1, LSL #16     ; Use High 16-bits
                STR     R4, [R0, R3]        ; Store into SIRx
                ADD     R1, R1, #4          ; Next IRQ Address
                ADD     R3, R3, #4          ; Next SIRx
                SUBS    R2, R2, #1          ; Decrement Counter
                BNE     EIC_Loop                               
                ENDIF


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                IF      :DEF:__MICROLIB

                EXPORT __initial_sp

                ELSE

                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size

                ENDIF


; Enter the C code

                IMPORT  __main
                LDR     R0, =__main
                BX      R0


                IF      :DEF:__MICROLIB

                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE
; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
                ENDIF


                END