📄 str73x.s
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;/*****************************************************************************/
;/* STARTUP.S: Startup file for ST STR73x device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The STARTUP.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set internal RAM is remapped to address 0. It replaces the
; * Flash memory normally accessible in this location. Even when remapped,
; * the RAM is also accessible at its physical address 0xA0000000.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000100
USR_Stack_Size EQU 0x00000400
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; System Configuration registers (CFG) definitions
CFG_BASE EQU 0x40000000 ; Configuration Registers Base Address
CFG_R0_OFS EQU 0x00 ; Configuration Register 0 Offset
CFG_PCGR0_OFS EQU 0x08 ; Periph Clock Gating Register 0 Offset
CFG_PCGR1_OFS EQU 0x0C ; Periph Clock Gating Register 1 Offset
CFG_PCGR0_Rst EQU 0x00000001 ; PCGR0 Peripherals Mask
CFG_PCGR1_Rst EQU 0x00000000 ; PCGR1 Peripherals Mask
;// <e> Reset all Device Peripherals (except RAM)
PERIPH_RESET EQU 0
;// </e>
; Enhanced Interrupt Controller (EIC) definitions
EIC_BASE EQU 0xFFFFFC00 ; EIC Base Address
ICR_OFS EQU 0x00 ; Interrupt Control Reg. Offset
CIPR_OFS EQU 0x08 ; Curr. Int. Priority R. Offset
IVR_OFS EQU 0x18 ; Interrupt Vector Reg. Offset
FIR_OFS EQU 0x1C ; Fast Interrupt Reg. Offset
IER0_OFS EQU 0x20 ; Interrupt Enable Reg. 0 Offset
IER1_OFS EQU 0x24 ; Interrupt Enable Reg. 1 Offset
IPR0_OFS EQU 0x40 ; Interrupt Pending Reg. 0 Offset
IPR1_OFS EQU 0x44 ; Interrupt Pending Reg. 1 Offset
SIR0_OFS EQU 0x60 ; Source Interrupt Reg. 0 Offset
;// <e> Setup EIC and Exception Handlers
EIC_SETUP EQU 1
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
EXPORT Vectors
AREA Reset, CODE, READONLY
ARM
IF EIC_SETUP <> 0
; Import Exceptions Handlers
IMPORT UndefHandler
IMPORT SWIHandler
IMPORT PAbtHandler
IMPORT DAbtHandler
IMPORT IRQHandler
IMPORT FIQHandler
; Import IRQ Handlers
IMPORT PRCCUCMUIRQHandler
IMPORT EXTIT01IRQHandler
IMPORT EXTIT02IRQHandler
IMPORT EXTIT03IRQHandler
IMPORT EXTIT04IRQHandler
IMPORT EXTIT05IRQHandler
IMPORT EXTIT06IRQHandler
IMPORT EXTIT07IRQHandler
IMPORT EXTIT08IRQHandler
IMPORT EXTIT09IRQHandler
IMPORT EXTIT10IRQHandler
IMPORT EXTIT11IRQHandler
IMPORT EXTIT12IRQHandler
IMPORT EXTIT13IRQHandler
IMPORT EXTIT14IRQHandler
IMPORT EXTIT15IRQHandler
IMPORT DMATRERRIRQHandler
IMPORT TIM1IRQHandler
IMPORT TIM2IRQHandler
IMPORT TIM3IRQHandler
IMPORT TIM4IRQHandler
IMPORT TB0IRQHandler
IMPORT TB1IRQHandler
IMPORT TB2IRQHandler
IMPORT TIM5IRQHandler
IMPORT TIM6IRQHandler
IMPORT TIM7IRQHandler
IMPORT TIM8IRQHandler
IMPORT TIM9IRQHandler
IMPORT UART2IRQHandler
IMPORT UART3IRQHandler
IMPORT FLASHEOPIRQHandler
IMPORT PWM0IRQHandler
IMPORT PWM1IRQHandler
IMPORT PWM2IRQHandler
IMPORT PWM3IRQHandler
IMPORT PWM4IRQHandler
IMPORT PWM5IRQHandler
IMPORT WIUIRQHandler
IMPORT WDGWUTIRQHandler
IMPORT BSPI0IRQHandler
IMPORT BSPI1IRQHandler
IMPORT BSPI2IRQHandler
IMPORT UART0IRQHandler
IMPORT UART1IRQHandler
IMPORT I2C0ITERRIRQHandler
IMPORT I2C1ITERRIRQHandler
IMPORT I2C0ITDDCIRQHandler
IMPORT I2C1ITDDCIRQHandler
IMPORT CAN0IRQHandler
IMPORT CAN1IRQHandler
IMPORT CAN2IRQHandler
IMPORT DMA0IRQHandler
IMPORT DMA1IRQHandler
IMPORT DMA2IRQHandler
IMPORT DMA3IRQHandler
IMPORT ADCIRQHandler
IMPORT RTCIRQHandler
ENDIF
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
IF EIC_SETUP <> 0
LDR PC,IRQ_Addr
ELSE
LDR PC,[PC, #-0x0408] ; Vector from EIC_IVR
ENDIF
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD UndefHandler
SWI_Addr DCD SWIHandler
PAbt_Addr DCD PAbtHandler
DAbt_Addr DCD DAbtHandler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQHandler
FIQ_Addr DCD FIQHandler
IF EIC_SETUP = 0
UndefHandler B UndefHandler
SWIHandler B SWIHandler
PAbtHandler B PAbtHandler
DAbtHandler B DAbtHandler
IRQHandler B IRQHandler
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