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<hr><p align="left"><small>发信人: doot (ltt), 信区: Embedded <br>
标 题: BDM手册5 <br>
发信站: BBS 水木清华站 (Thu Oct 26 16:23:32 2000) <br>
<br>
Embedded PowerPC BDM (Motorola MPC5xx, MPC8xx) <br>
This BDM works quite differently from the CPU32 type of BDM. The hardware in <br>
terface <br>
is similar with serial in, serial out, clock, reset, and status signals. The <br>
difference is that <br>
there is not a specific command set. Any serial stream entered into the chip <br>
is either 7 or <br>
32 bits in length (not counting start, control, and length bits). Thirty- tw <br>
o- bit bit streams <br>
go into the instruction stuff register and come out of the debug data regist <br>
er. What <br>
actually happens is that the host debugger stuffs PowerPC opcodes into the p <br>
rocessor and <br>
they are executed. This is actually a very powerful design allowing for all <br>
system resources <br>
to be accessible since this method gives the debug port the same power as ex <br>
ecuting <br>
system code. Seven bit data streams are used to control on chip breakpoint f <br>
unctions. <br>
unctions. <br>
Debug control registers exist to enable single stepping and other special co <br>
ntrols. <br>
The processor is “aware” of this BDM in that it is a CPU exception. BDM ma <br>
y be entered <br>
upon one of any number of exception causing events (invalid opcode, address <br>
bus <br>
misalignment, non- maskable interrupt, etc.) To resume real- time execution, <br>
the debugger <br>
stuffs a “return from exception” instruction, “RFI” into the processor’ <br>
s instruction register. <br>
OnCE (On- Chip Emulation) <br>
The OnCE (On- Chip Emulation) interface is found on Motorola’s family of DS <br>
P chips. It <br>
allows for all the same type of debugging as the BDM interface. On most of t <br>
he chips, the <br>
OnCE interface is implemented via dedicated pins. On the more recent parts, <br>
the OnCE <br>
engine is accessed via the JTAG port pins. The OnCE port is more complex tha <br>
n the BDM <br>
port in that it is a state machine controlled by the external debugger. The <br>
capabilities of <br>
OnCE include: <br>
OnCE include: <br>
Interrupt/ break into debug mode on program memory address <br>
Interrupt/ break into debug node on data memory address <br>
Interrupt/ break into debug mode on an on- chip peripheral access <br>
Enter debug mode using a DSP microprocessor instruction <br>
Read/ write any DSP core register <br>
Read/ write peripheral memory mapped registers <br>
Read/ write program or data memory <br>
Step one or more instructions <br>
Trace one or more instructions <br>
Save or restore current chip pipeline <br>
Read real- time instruction trace buffer <br>
Exit debug mode <br>
JTAG debugging (PPC6xx, IBM 4xx, TI C90, Analog Devices SHARC) <br>
JTAG (Joint Test Action Group. pronounced “jay- tag”) is an IEEE specifica <br>
tion (IEEE <br>
1149.1). It is actually a method for doing full chip testing and was origina <br>
lly implemented <br>
to allow testing of all the pin connections of a chip and its interconnectio <br>
ns to other chips <br>
on the circuit board. It is a serial protocol and chips on the board may be <br>
daisy- chained <br>
together. In simple terms, the JTAG serial chain through the chip may be wir <br>
ed through <br>
any on chip devices but typically minimally connects to all the I/ O pins an <br>
d buffers. The <br>
chain may be several score long or thousands of elements. There is no specif <br>
ication stating <br>
any inclusion of resources for software debug nor is there a prohibition. <br>
Different processors implement OCD via JTAG in different ways. The 600 serie <br>
s of PowerPC <br>
microprocessors purely use the hardware test chain which winds its way throu <br>
gh many of <br>
the on- chip resources. Somewhere in the multi- thousand stage serial chain <br>
is the instruction <br>
register, for example. Debugging with this system is tedious since each core <br>
OCD action <br>
(modify memory location for instance) may take many trips through the entire <br>
JTAG <br>
chain. Although the debugger may only be interested in a 32 bit piece of the <br>
chain, all <br>
elements must be traversed, and multiple times. Downloading user code may be <br>
as slow as <br>
less than one hundred bytes per second (vs. over 20K per second with other m <br>
ethods). <br>
ethods). <br>
Another drawback to implementations that use a shared hardware test/ softwar <br>
e debug <br>
chain (TI DSP chips, 600 family PowerPC, etc.) is the way the chain is route <br>
d during chip <br>
design. Since this is typically the least critical path and the least critic <br>
al part of the chip <br>
design/ layout (as well it should be), the designers let the silicon auto- r <br>
outer layout the <br>
chain’s pathway after the rest of the chip has been laid out. This means th <br>
at each revision <br>
of the silicon may have a different JTAG chain, hence the host debugger soft <br>
ware must be <br>
aware of every revision of silicon. This is a nightmare. TI solves this prob <br>
lem by often <br>
updating their OEM emulator software tool kit. This does not help the end- u <br>
ser unless <br>
he/ she has a very reliable debugger vendor. <br>
An alternative method to the JTAG OCD is to use a different chain via the JT <br>
AG port. <br>
This is allowed for in the IEEE specification. Using this method, one chain <br>
is available for <br>
the hardware test and debug of the chip, another for software debug. This me <br>
thod is used <br>
in the IBM 400 series of PowerPC as well as in the SHARC DSP from Analog Dev <br>
ices. <br>
This secondary chain allows access to debug specific registers, usually only <br>
two or three <br>
are needed. In the IBM chips, the debug port has access to an instruction st <br>
uff buffer, a <br>
debug control register and a debug status register. The instruction stuff bu <br>
ffer allows the <br>
debugger to stuff any opcode into the core processors’ instruction register <br>
, in effect causing <br>
a single step to occur. By executing the proper instructions, any action nee <br>
ded may be <br>
performed. The debug control and status registers allow for the typical debu <br>
g commands <br>
such as single step and run. Since a chain separate from the hardware test c <br>
hain is used, <br>
the length of the chain is typically under 50 bits long. There is some small <br>
overhead with <br>
each JTAG action to ensure that the proper chain is being accessed. <br>
Note that TI uses different flavors of the JTAG port on the DSP chips. The C <br>
30 family <br>
actually has what is referred to as an MPSD port, similar but not exactly JT <br>
AG. <br>
An advantage to using the JTAG port for software debug is that it does not n <br>
eed any <br>
additional pins on the processor for separate hardware and software debug. A <br>
disadvantage <br>
is the added overhead needed for each basic action. <br>
<br>
-- <br>
<br>
※ 来源:·BBS 水木清华站 smth.org·[FROM: 202.117.114.7] <br>
</small><hr>
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