450.htm

pcb设计资料初学者难得的入门资料包含工厂制作过程

A method of interfacing with hardware that involves repeatedly reading a sta <br>
tus <br>
register until the device has reached the awaited state. Device drivers are <br>
either <br>
polling or interrupt-driven, with the latter being more generally preferred. <br>
  <br>
priority <br>
The relative importance of one task compared to another. <br>
priority inversion <br>
An unwanted software situation in which a high-priority task is delayed whil <br>
e <br>
waiting for access to a shared resource that is not even being used at the t <br>
ime. <br>
For all practical purposes, the priority of this task has been lowered durin <br>
g the <br>
delay period. <br>
process <br>
A word that is often confused with task or thread. The crucial distinction i <br>
s that <br>
all of the tasks in a system share a common memory space. Processes, on the <br>
other <br>
hand, always have their own private memory space. Processes are common in <br>

multi-user systems but are rarely, if ever, found in embedded systems. <br>
processor <br>
A generic term that does not distinguish between microprocessor, microcontro <br>
ller, <br>
and digital signal processor. <br>
processor family <br>
A set of related processors, usually successive generations from the same <br>
manufacturer. For example, Intel's 80x86 family began with the 8086 and now <br>
includes the 80186, 286, 386, 486, Pentium, and many others. The later model <br>
s in a <br>
family are typically backwards-compatible with the ones that came before. <br>
processor-independent <br>
A piece of software that is independent of the processor on which it will be <br>
 run. <br>
Most programs that can be written in a high-level language are <br>
processor-independent. Contrast with processor-specific. <br>
processor-specific <br>
A piece of software that is highly dependent on the processor on which it wi <br>
ll be <br>
run. Such code must usually be written in assembly language. Contrast with <br>
processor-independent. <br>
profiler <br>
profiler <br>
A software development tool that collects and reports execution statistics f <br>
or <br>
your programs. These statistics include the number of calls to each subrouti <br>
ne and <br>
the total amount of time spent within each. This data can be used to learn w <br>
hich <br>
subroutines are the most critical and, therefore, demand the greatest code <br>
efficiency. <br>
program counter <br>
See instruction pointer. <br>
R <br>
RAM <br>
Random-Access Memory. A broad classification of memory devices that includes <br>
  <br>
all devices in which individual memory locations may be read or written as r <br>
equired. <br>
RISC <br>
Reduced Instruction Set Computer. Describes the architecture of a processor <br>
family. RISC processors generally feature fixed-length instructions, a load- <br>
store <br>
memory architecture, and a large number of general-purpose registers and/or <br>
register windows. The MIPS processor family is an excellent example. Contras <br>

t <br>
with CISC. <br>
ROM <br>
Read-Only Memory. A broad classification of memory devices that includes all <br>
  <br>
devices in which the individual memory locations may be read, but not writte <br>
n. <br>
ROM emulator <br>
A debugging tool that takes the place of-or emulates-the ROM on your target <br>
board. A ROM emulator acts very much like a debug monitor, except that it <br>
includes its own serial or network connection to the host. <br>
ROM monitor <br>
See debug monitor. <br>
RTOS <br>
Real-Time Operating System. An operating system designed specifically for us <br>
e in <br>
real-time systems. <br>
race condition <br>
A situation in which the outcome of a program may be affected by the exact o <br>
rder <br>
in which the instructions are executed. Race conditions are only an issue wh <br>
ere <br>
ere <br>
interrupts and/or preemption are possible and where critical sections exist. <br>
  <br>
real-time system <br>
Any computer system, embedded or otherwise, that has deadlines. The followin <br>
g <br>
question can be used to distinguish real-time systems from the rest: "Is a l <br>
ate <br>
answer as bad, or even worse, than a wrong answer?" In other words, what hap <br>
pens <br>
if the computation doesn't finish in time? If nothing bad happens, it's not <br>
a <br>
real-time system. If someone dies or the mission fails, it's generally consi <br>
dered <br>
"hard" real-time, which is meant to imply that the system has "hard" deadlin <br>
es. <br>
Everything in between is "soft" real-time. <br>
recursive <br>
Said of software that calls itself. Recursion should generally be avoided in <br>
 an <br>
embedded system, since it frequently requires a large stack. <br>
reentrant <br>
Said of software that can be executed multiple times simultaneously. A reent <br>

rant <br>
function can be safely called recursively or from multiple tasks. The key to <br>
 making <br>
code reentrant is to ensure mutual exclusion whenever accessing global varia <br>
bles <br>
or shared registers. <br>
register <br>
A memory location that is part of a processor or an I/O device. In other wor <br>
ds, <br>
it's not normal memory. Generally, each bit or set of bits within the regist <br>
er <br>
controls some behavior of the larger device. <br>
relocatable <br>
A file containing object code that is almost ready for execution on the targ <br>
et. The <br>
final step is to use a locator to fix the remaining relocatable addresses wi <br>
thin the <br>
code. The result of that process is an executable. <br>
reset address <br>
The address from which the first instruction will be fetched after the proce <br>
ssor <br>
is powered on or reset. <br>

reset code <br>
A small piece of code that is placed at the reset address. The reset code is <br>
 usually <br>
written in assembly language and may simply be the equivalent of "jump to th <br>
e <br>
startup code." <br>
reset vector <br>
See reset address. <br>
S <br>
SRAM <br>
Static Random-Access Memory. A type of RAM that retains its contents as long <br>
 as <br>
the system is powered on. Data stored in an SRAM is lost when the system is <br>
powered down or reset. <br>
scheduler <br>
The part of an operating system that decides which task to run next. This de <br>
cision <br>
is based on the readiness of each task, their relative priorities, and the s <br>
pecific <br>
scheduling algorithm implemented. <br>
semaphore <br>
A data structure that is used for intertask synchronization. Semaphores are <br>

usually provided by the operating system. <br>
simulator <br>
A debugging tool that runs on the host and pretends to be the target process <br>
or. A <br>
simulator can be used to test pieces of the software before the embedded <br>
hardware is available. Unfortunately, attempts to simulate interactions with <br>
  <br>
complex peripherals are often more trouble than they are worth. <br>
software interrupt <br>
An interruption of a program that is initiated by a software instruction. So <br>
ftware <br>
interrupts are commonly used to implement breakpoints and operating system <br>
entry points. Unlike true interrupts, they occur synchronously with respect <br>
to <br>
program execution. In other words, software interrupts always occur at the <br>
beginning of an instruction execution cycle. Compare with trap. <br>
stack <br>
An area of memory that contains a last-in-first-out queue of storage for <br>
parameters, automatic variables, return addresses, and other information tha <br>
t <br>
must be maintained across function calls. In multitasking situations, each t <br>
ask <br>
ask <br>
generally has its own stack. <br>
stack frame <br>
An area of the stack associated with a particular function call. <br>
startup code <br>
A piece of assembly language code that prepares the way for software written <br>
 in a <br>
high-level language. Most C/C++ cross-compilers come with startup code that <br>
you <br>
can modify, compile, and link with your embedded programs. <br>
T <br>
target <br>
Another name for the embedded system. This term is usually used during softw <br>
are <br>
development, to distinguish the embedded system from the host with which it <br>
communicates. <br>
task <br>
The central abstraction of an operating system. Each task must maintain its <br>
own <br>
copy of the instruction pointer and general-purpose registers. Unlike proces <br>
ses, <br>
tasks share a common memory space and must be careful to avoid overwriting e <br>
ach <br>
ach <br>
other's code and data. <br>
thread <br>
Another name for a task. This name is more common in operating systems that <br>
support processes. A task is simply a thread in a single-process system. <br>
tracepoint <br>
Like a breakpoint except that a counter is incremented rather than stopping <br>
the <br>
program. Tracepoints are not supported by all debugging tools. <br>
trap <br>
An interruption of a program that is triggered by the processor's own intern <br>
al <br>
hardware. For example, the processor might trap if an illegal opcode is foun <br>
d <br>
within the program. Compare with software interrupt. <br>
V <br>
volatile <br>
A value that may change without the intervention of software is said to be v <br>
olatile. <br>
For example, values within the registers of some I/O devices may change in <br>
response to external events. C's volatile keyword should be used to warn you <br>
r <br>
compiler about any pointers that point to such registers. This will ensure t <br>

hat the <br>
actual value is reread each time the data is used. <br>
W <br>
watchdog timer <br>
A hardware timer that is periodically reset by software. If the software cra <br>
shes <br>
or hangs, the watchdog timer will expire, and the entire system will be rese <br>
t <br>
automatically. <br>
  <br>
-- <br>
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