item_new2.map.qmsg

项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 22 14:34:16 2008 " "Info: Processing started: Fri Aug 22 14:34:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off item_new2 -c item_new2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off item_new2 -c item_new2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "item_new2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file item_new2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 item_new2-a " "Info: Found design unit 1: item_new2-a" {  } { { "item_new2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 item_new2 " "Info: Found entity 1: item_new2" {  } { { "item_new2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "item_new2 " "Info: Elaborating entity \"item_new2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "itemnew3_2.vhd 2 1 " "Warning: Using design file itemnew3_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 itemnew3_2-a " "Info: Found design unit 1: itemnew3_2-a" {  } { { "itemnew3_2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 itemnew3_2 " "Info: Found entity 1: itemnew3_2" {  } { { "itemnew3_2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "itemnew3_2 itemnew3_2:u2 " "Info: Elaborating entity \"itemnew3_2\" for hierarchy \"itemnew3_2:u2\"" {  } { { "item_new2.vhd" "u2" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "once itemnew3_2.vhd(24) " "Warning (10492): VHDL Process Statement warning at itemnew3_2.vhd(24): signal \"once\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "itemnew3_2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "once_1 itemnew3_2.vhd(39) " "Warning (10492): VHDL Process Statement warning at itemnew3_2.vhd(39): signal \"once_1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "itemnew3_2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd" 39 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } {  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "207 " "Info: Implemented 207 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "192 " "Info: Implemented 192 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 22 14:34:20 2008 " "Info: Processing ended: Fri Aug 22 14:34:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}