example 3-7.asm

TI_DSP在音频处理中的应用,滤波器算法等各种常用算法。

	SSXM ;allow sign extension
	CLRCCNF ;Config Block B0 to Data mem.
	LACC#COS45K
	SACLCOS45 ;Init location with constant.

;-----------------------------------
; Set up PLL Module
;-----------------------------------

	LDP #00E0h ;DP = 224; Address 7000h - 707Fh
			;The following line is necessary if a previous program set the PLL to a different
			;setting than the settings which the application uses. By disabling the PLL, the
			;CKCR1 register can be modified so that the PLL can run at the new settings when
			;it is re-enabled.
			; 5432109876543210
	SPLK	#0000000001000001b,CKCR0 ;CLKMD=PLL Disable,SYSCLK=CPUCLK/2
					; 5432109876543210
	SPLK	#0000000010111011b,CKCR1 ;CLKIN(OSC)=10MHz,CPUCLK=20MHz
			;CKCR1 - Clock Control Register 1
			; Bits 7-4 (1011)CKINF(3)-CKINF(0) - Crystal or Clock-In Frequency
			; Frequency = 10MHz
			; Bit 3 (1) PLLDIV(2) - PLL divide by 2 bit
			; Divide PLL input by 2
			; Bits 2-0 (011) PLLFB(2)-PLLFB(0) - PLL multiplication ratio
			; PLL Multiplication Ratio = 4
			; 5432109876543210
	SPLK	#0000000011000001b,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2
			;CKCR0 - Clock Control Register 0
			; Bits 7-6 (11)CLKMD(1),CLKMD(0) - Operational mode of Clock Module
			; PLL Enabled; Run on CLKIN on exiting low power mode
			; Bits 5-4 (00)PLLOCK(1),PLLOCK(0) - PLL Status. READ ONLY
			; Bits 3-2 (00)PLLPM(1),PLLPM(0) - Low Power Mode
			; LPM0
			; Bit 1 (0) ACLKENA - 1MHz ACLK Enable
			; ACLK Disabled
			; Bit 0 (1) PLLPS - System Clock Prescale Value
			; f(sysclk)=f(cpuclk)/2
			; 5432109876543210
	SPLK	#0100000011000000b,SYSCR ;CLKOUT=CPUCLK
			;SYSCR - System Control Register
			; Bit 15-14 (01)RESET1,RESET0 - Software Reset Bits
			; No Action
			; Bits 13-8 (000000) Reserved
			; Bit 7-6(11)CLKSRC1,CLKSRC0 - CLKOUT-Pin Source Select
			; CPUCLK: CPU clock output mode
			; Bit 5-0(000000) Reserved
	SPLK	#006Fh, WDCR ;Disable WD if VCCP=5V (JP5 in pos. 2-3)
	KICK_DOG ;Reset Watchdog

;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
;- Event Manager Module Reset 						*
;									* 
;- This section resets all of the Event Manager Module Registers.	*
;* This is necessary for silicon revsion 1.1; however, for 		*
;- silicon revisions 2.0 and later, this is not necessary 		*
;									* -
;- 									*
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

	LDP 	#232 ;DP=232 Data Page for the Event Manager
	SPLK	#0000h,GPTCON ;Clear General Purpose Timer Control
	SPLK	#0000h,T1CON ;Clear GP Timer 1 Control
	SPLK	#0000h,T2CON ;Clear GP Timer 2 Control
	SPLK	#0000h,T3CON ;Clear GP Timer 3 Control
	SPLK	#0000h,COMCON ;Clear Compare Control
	SPLK	#0000h,ACTR ;Clear Full Compare Action Control Register
	SPLK	#0000h,SACTR ;Clear Simple Compare Action Control Register
	SPLK	#0000h,DBTCON ;Clear Dead-Band Timer Control Register
	SPLK	#0FFFFh,EVIFRA;Clear Interrupt Flag Register A
	SPLK	#0FFFFh,EVIFRB;Clear Interrupt Flag Register B

	SPLK	#0FFFFh,EVIFRC;Clear Interrupt Flag Register C
	SPLK	#0000h,CAPCON ;Clear Capture Control
	SPLK	#0000h,EVIMRA ;Clear Event Manager Mask Register A
	SPLK	#0000h,EVIMRB ;Clear Event Manager Mask Register B
	SPLK	#0000h,EVIMRC ;Clear Event Manager Mask Register C

;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
;- End of RESET section for silicon revision 1.1 *
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
;-----------------------------------
; Set up Event Manager Module
;-----------------------------------

T1COMPARE .set78
T1PERIOD .set156 ;Sets up period for 128kHz frequency
		;T1COMPARE .set156
		;T1PERIOD .set313 ;Sets up period for 64kHz frequency
		;T1COMPARE .set500
		;T1PERIOD .set1000 ;Sets up period for 20kHz frequency
	LDP #232 ;DP=232, Data Page for Event Manager Addresses
	SPLK	#T1COMPARE,T1CMPR ;T1CMPR set up for 50% duty cycle
		; 2109876543210
	SPLK	#0000001010101b,GPTCON
		;GPTCON - GP Timer Control Register
		; Bit 15 (0) T3STAT - GP Timer 3 Status. READ ONLY
		; Bit 14 (0) T2STAT - GP Timer 2 Status. READ ONLY
		; Bit 13 (0) T1STAT - GP Timer 1 Status. READ ONLY
		; Bits 12-11 (00)T3TOADC - ADC start by event of GP Timer 3
		; No event starts ADC
		; Bits 10-9 (00)T2TOADC - ADC start by event of GP Timer 2
		; No event starts ADC
		; Bits 8-7 (00)T1TOADC - ADC start by event of GP Timer 1
		; No event starts ADC
		; Bit 6 (1) TCOMPOE - Compare output enable
		; Enable all three GP timer compare outputs
		; Bits 5-4 (01)T3PIN - Polarity of GP Timer 3 compare output
		; Active Low
		; Bits 3-2 (01)T2PIN - Polarity of GP Timer 2 compare output
		; Active Low
		; Bits 1-0 (01)T1PIN - Polarity of GP Timer 1 compare output
		; Active Low
	SPLK	#T1PERIOD,T1PR ;T1PR = T1PERIOD value for Sampling Freq.
	SPLK	#0000h,T1CNT ;Clear GP Timer 1 Counter
	SPLK	#0000h,T2CNT ;Clear GP Timer 2 Counter
	SPLK	#0000h,T3CNT ;Clear GP Timer 3 Counter
		; 5432109876543210
	SPLK	#0001000001000010b,T1CON
		;T1CON - GP Timer 1 Control Register
		; Bits 15-14 (00)FREE,SOFT - Emulation Control Bits
		; Stop immediately on emulation suspend
		; Bits 13-11 (010) TMODE2-TMODE0 - Count Mode Selection
		; Continuous-Up Count Mode
		; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler

		; Divide by 1
		; Bit 7 (0) Reserved
		; Bit 6 (0) TENABLE - Timer Enable
		; Disable timer operations
		; Bits 5-4 (00)TCLKS1,TCLKS0 - Clock Source Select
		; Internal Clock Source
		; Bits 3-2 (00)TCLD1,TCLD0 - Timer Compare Register Reload Condition
		; When counter is 0
		; Bit 1 (1) TECMPR - Timer compare enable
		; Enable timer compare operation
		; Bit 0 (0) Reserved
		; 5432109876543210
	SPLK	#0000000000000000b,T2CON ;GP Timer 2 - Not Used
		;T2CON - GP Timer 2 Control Register
		; Bits 15-14 (00)FREE,SOFT - Emulation Control Bits
		; Stop immediately on emulation suspend
		; Bits 13-11 (000) TMODE2-TMODE0 - Count Mode Selection
		; Stop/Hold
		; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler
		; Divide by 1
		; Bit 7 (0) TSWT1 - GP Timer 1 timer enable bit
		; Use own TENABLE bit
		; Bit 6 (0) TENABLE - Timer Enable
		; Disable timer operations
		; Bits 5-4 (00)TCLKS1,TCLKS0 - Clock Source Select
		; Internal Clock Source
		; Bits 3-2 (00)TCLD1,TCLD0 - Timer Compare Register Reload Condition
		; When counter is 0
		; Bit 1 (0) TECMPR - Timer compare enable
		; Disable timer compare operation
		; Bit 0 (0) SELT1PR - Period Register select
		; Use own period register
		; 5432109876543210
	SPLK	#0000000000000000b,T3CON ;GP Timer 3 - Not Used
		;T3CON - GP Timer 3 Control Register
		; Bits 15-14 (00)FREE,SOFT - Emulation Control Bits
		; Stop immediately on emulation suspend
		; Bits 13-11 (000) TMODE2-TMODE0 - Count Mode Selection
		; Stop/Hold
		; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler
		; Divide by 1
		; Bit 7 (0) TSWT1 - GP Timer 1 timer enable bit
		; Use own TENABLE bit
		; Bit 6 (0) TENABLE - Timer Enable
		; Disable timer operations
		; Bits 5-4 (00)TCLKS1,TCLKS0 - Clock Source Select
		; Internal Clock Source
		; Bits 3-2 (00)TCLD1,TCLD0 - Timer Compare Register Reload Condition
		; When counter is 0
		; Bit 1 (0) TECMPR - Timer compare enable
		; Disable timer compare operation
		; Bit 0 (0) SELT1PR - Period Register select
		; Use own period register

;-----------------------------------
; Set up Digital I/O Port
;-----------------------------------
	LDP #225 ;DP = 225; Addresses 7800h to 707Fh
		; 5432109876543210
	SPLK	#0011100000001111b,OCRA
		;OCRA - Output Control Register A
		; Bit 15 (0) CRA.15 - IOPB7
		; Bit 14 (0) CRA.14 - IOPB6
		; Bit 13 (1) CRA.13 - T3PWM/T3CMP
		; Bit 12 (1) CRA.12 - T2PWM/T2CMP
		; Bit 11 (1) CRA.11 - T1PWM/T1CMP
		; Bit 10 (0) CRA.10 - IOPB2
		; Bit 9 (0) CRA.9 - IOPB1
		; Bit 8 (0) CRA.8 - IOPB0
		; Bits 7-4 (0000)Reserved
		; Bit 3 (1) CRA.3 - ADCIN8
		; Bit 2 (1) CRA.2 - ADCIN9
		; Bit 1 (1) CRA.1 - ADCIN1
		; Bit 0 (1) CRA.0 - ADCIN0
		; 76543210
	SPLK	#11110000b,OCRB
		;OCRB - Output Control Register B
		; Bit 7 (1) CRB.7 - CAP4
		; Bit 6 (1) CRB.6 - CAP3
		; Bit 5 (1) CRB.5 - CAP2/QEP2
		; Bit 4 (1) CRB.4 - CAP1/QEP1
		; Bit 3 (0) CRB.3 - BIO
		; Bit 2 (0) CRB.2 - XF
		; Bit 1 (0) CRB.1 - ?
		; Bit 0 (0) CRB.0 - IOPC0

;-----------------------------------
; Set up ADC Module
;-----------------------------------
	LDP 	#224 ;DP = 224 Data Page for ADC Registers
		; 5432109876543210
	SPLK	#1000100100000000b,ADCTRL1
		;ADCTRL1 - ADC Control Register 1
		; Bit 15 (1) Suspend-SOFT -
		; Complete Conversion before halting emulator
		; Bit 14 (0) Suspend-FREE -
		; Operations is determined by Suspend-SOFT
		; Bit 13 (0) ADCIMSTART - ADC start converting immediately
		; Immediate Start of Conversion
		; Bit 12 (0) ADC1EN - Enable/Disable ADC2
		; Disable ADC2
		; Bit 11 (1) ADC2EN - Enable/Disable ADC1
		; Enable ADC1
		; Bit 10 (0) ADCCONRUN - ADC Continuous Conversion Mode
		; Disable Continuous Conversion
		; Bit 9 (0) ADCINTEN - Enable ADC Interrupt
		; No action when ADCINTFLAG is set
		; Bit 8 (1) ADCINTFLAG - ADC Interrupt Flag
		; Clear Interrupt Flab Bit
		; Bit 7 (0) ADCEOC - End of Conversion Bit READ ONLY
		; Bits 6-4 (000) ADC2CHSEL - ADC2 Channel Select
		; Channel 8
		; Bits 3-1 (000) ADC1CHSEL - ADC1 Channel Select
		; Channel 0
		; Bit 0 (0) ADCSOC - ADC Start of conversion bit
		; No Action

		; 5432109876543210
	SPLK	#0000000000000101b,ADCTRL2
		;ADCTRL2 - ADC Control Register 2
		; Bits 15-11 (00000)Reserved
		; Bit 10 (0) ADCEVSOC - Event Manager SOC mask bit
		; Mask ADCEVSOC
		; Bit 9 (0) ADCEXTSOC - External SOC mask bit
		; Mask ADCEXTSOC
		; Bit 8 (0) Reserved
		; Bits 7-6 (00)ADCFIFO1 - Data Register FIFO1 Status READ ONLY
		; Bit 5 (0) Reserved
		; Bits 4-3 (00)ADCFIFO2 - Data Register FIFO2 Status READ ONLY
		; Bits 2-0 (101) ADCPSCALE - ADC Input Clock Prescaler
		; Prescale Value 16
		; SYSCLK Period = 0.1usec
		; 0.1usec x 16 x 6 = 9.6 usec >= 6usec
		;The DAC module requires that wait states be generated for proper operation.
	LDP #0000h ;Set Data Page Pointer to 0000h, Block B2
	SPLK	#4h,GPR0 ;Set Wait State Generator for
	OUT GPR0,WSGR ;Program Space, 0WS
		;Date Space, 0WS
		;I/O Space, 1WS

;==============================================================================
; Xfer the Twiddles to RAM Block B1 (# Twiddles = 96)
;==============================================================================

	REPEAT LAR AR0, #95 ;set # of Twiddles to Xfer
	LAR AR1, #B1_SADR ;AR1 points to 1st dest DM addr
	LACC#PS_TWID_STRT ;ACC points to 1st Src PM addr
	TWD_XFR MAR *,1 ;select AR1
	TBLR*+, AR0 ;Mov Prog word --> Data mem
	ADD #1 ;inc ACC
	BANZTWD_XFR ;continue Xfer until AR0=0


;==============================================================================
; Fetch 128 Data sample points from I/O port 0
;==============================================================================
	FTCH_DATA LAR AR0, #128 ;AR0 = 128; # of Samples for Bit Reversed Addressing
	LAR AR1, #B0_SADR ;AR1 = Start Address of B0; Data Buffer
	LAR AR2, #ADCFIFO1 ;AR2 = Value Converted from ADC
	LAR AR3, #(B1_SADR+128) ;AR3 = B1_SADR + 128
	LAR AR7, #127 ;AR7 = 128 - 1
	MAR *, AR2 ;ARP = AR2
	LDP #224 ;Set Bit 0 of ADCTRL1
	SBIT1 ADCTRL1,B0_MSK ;Starts ADC converting
	LDP #232 ;Set Bit 6 of T1CON
	SBIT1 T1CON,B6_MSK ;Starts the GP Timer 1


;=========================================================================
; Correction is made in the following data collection section
; 10 Jun 99
;=========================================================================
	CLRCSXM ; Disable sign extension mode
		; while reading in data from ADC
	FTCH_LPBIT EVIFRA,BIT7 ;Polling routine to wait for
	BCNDFTCH_LP,NTC ;T1PINT Flag to be Set
	LDP #224
	SBIT1 ADCTRL1,B0_MSK ;Restart the ADC
	LACC *,15,AR3 ;ACC = ADCFIFO1; ARP = AR3
	SACH*+,0,AR1 ;Value at location pointed by AR3
		;= Value pointed to by AR2; ARP = AR1
	SACH*BR0+,0,AR7 ;Store sample into data buffer of B0 using
		;bit reversed addressing; ARP = AR7
	LDP #232
	LACCEVIFRA ;ACC = Event Manager Interrupt Flag Register
	SACLEVIFRA ;Clear the flag register
	BANZFTCH_LP,*-,AR2 ;Wait for next flag of T1PINT, or if 128
		;samples have been collected, perform FFT.
		;ARP = AR2
	SBIT0 T1CON,B6_MSK ;Stop GP timer 1 - for FFT
	SPLK	#0000h,T1CNT ;Clear GP timer 1 counter
	SETCSXM ; Enable sign extension mode


;==============================================================================
; Stages 1 & 2 - using the Radix 4 COMBO Macro
;==============================================================================
	MAR *, AR3
	LAR AR0, #7h ;Increment for Data pointers
	LAR AR1, #(B0_SADR)
	LAR AR2, #(B0_SADR+2)
	LAR AR3, #(B0_SADR+4)
	LAR AR4, #(B0_SADR+6)
	LAR AR5, #B2_SADR ;Gen purp reg @ 60h
	LAR AR7, #(N/4-1) ;Loop 32 times
	STAGE1_2_LP:
	COMBO
	BANZ STAGE1_2_LP,*-,AR3


;==============================================================================
; Stage 3 - using ZEROI, PBY4I, PBY2I, P3BY4I Macros
;==============================================================================
STAGE3:
	MAR *, AR2 ;ARP-->AR2
	LAR AR0, #9h ;
	LAR AR1, #(B0_SADR) ;-->P
	LAR AR2, #(B0_SADR+8) ;-->Q
	LAR AR5, #B2_SADR ;Gen purp reg @ 60h
	LAR AR7, #(N/8-1) ;Loop counter (32 times)
	LT COS45
STAGE3_LP:
	ZEROI
	PBY4I
	PBY2I
	P3BY4I 7,0 ;-->AR7 at end, use *0+ modify.
	BANZ STAGE3_LP,*-,AR2

;==============================================================================
; Stage 4 - using ZEROI, PBY4I, PBY2I, P3BY4I, BFLY Macros
;==============================================================================
STAGE4:
	MAR *, AR2 ;ARP-->AR2
	LAR AR0, #16 ;Used to inc Twiddle pointers
	LAR AR1, #(B0_SADR) ;-->P
	LAR AR2, #(B0_SADR+16) ;-->Q
	LAR AR5, #B2_SADR ;Gen purp reg @ 60h
	LAR AR7, #(N/16-1) ;Loop counter (8 times)
STAGE4_LP:
	ZEROI
	LAR AR3, #(TWID_TBL+8+N/4)
	LAR AR4, #(TWID_TBL+8)
	STG4_B1 BFLY 2
	LT COS45
	PBY4I
	STG4_B2 BFLY 2
	PBY2I
	STG4_B3 BFLY 2
	LT COS45
	P3BY4I 2, ;-->AR2 at end
	STG4_B4 BFLY 1
	ADRK#16
	MAR *, AR2
	ADRK#16
	MAR *, AR7
	BANZ	STAGE4_LP,*-,AR2


;==============================================================================