app_common.tci

Introduce how to Change the DVEVM6446 Memory Map

/*
 *  ======== app_common.tci ========
 *
 *  This script, common for all DSP application examples, configures DSP
 *  application's BIOS based on the application platform. The platform
 *  is determined by environment["config.platform"] variable which is set
 *  by the application's build script, to one of the following:
 *
 *  "ti.platforms.evmDM6446",
 *  "ti.platforms.evmDM6437", or
 *  "ti.platforms.evmDM648"
 */

var platform = environment["config.platform"];
//print("app_common.tci: platform = " + platform);

//
// Specify platform specific memory segment addresses and sizes, and other
// fields that need to be passed as params when loading the generic
// platform. Specifically, we need to set the following values:
//     ddrBase     - Base address of memory segment "DDR2"
//     ddrLen      - Length of "DDR2"
//     clockRate   - clock rate for the device
//     deviceName  - name of the device
//
// Values for clockRate and deviceName can be found Platform.tci file for
// the device (eg, in ti/platforms/evmDM6446/Platform.tci)
//
var platformParams = {
    "ti.platforms.evmDM6446" : {
        l1DMode : null,
        ddrBase : 0x8FA00000,
        ddrLen  : 0x400000,
        clockRate : 567,
        deviceName : "DM6446",
        l1dHeapSize: 0xC000,  // 48k: size to use for L1DHEAP in L1DSRAM
    },
    "ti.platforms.evmDM6437" : {
        l1DMode : null,
        ddrBase : 0x87A00000,
        ddrLen  : 0x00400000,
        clockRate : 594,
        deviceName : "DM6437",
        l1dHeapSize: 0xC000, // 48k: size to use for L1DHEAP in L1DSRAM
    },
    "ti.platforms.evmDM648" : {
        //
        //  DM648 has 32KB of L1D SRAM/Cache. Set L1DMode to value that
        //  won't cause L1DSRAM segment to be destroyed upon platform
        //  initialization. Values of "0k", "4k", "8k", and "16k" for
        //  L1DMode will prevent L1DSRAM from being destroyed, while
        //  leaving it undefined or setting it to null or "32k", will
        //  cause it to be destroyed (see function setupCache6452()
        //  in bios_6452.tci)
        //
        l1DMode : "8k",
        ddrBase : 0xE7A00000,
        ddrLen  : 0x00400000,
        clockRate : 700,
        deviceName : "DM648",
        l1dHeapSize: 0x6000,  // 24k: size to use for L1DHEAP in L1DSRAM
    },
};

if (platformParams[platform] == null) {
    throw("Unsupported platform: " + platform);
}

var params = platformParams[platform];

//print("app_common.tci: params.ddrBase = " + utils.toHex(params.ddrBase));

var mem_ext = [
{
    comment:    "DDR2: off-chip memory for code and data",
    name:       "DDR2",
    base:       platformParams[platform].ddrBase,
    len:        platformParams[platform].ddrLen,
    space:      "code/data"
},
];


/*
 *  Internal memory partitioning (for DM6446 -- may be different for other
 *  devices)
 *
 *  On the left in the diagram below is the layout of internal memory
 *  available on DM6446 for data caching and as RAM; on the right is the
 *  diagram showing how this configuration file partitions the available
 *  64k+80k of memory. (The 32K for program cache is not affected by this
 *  configuration.) Please find more specifics on how the configuration is
 *  done further below.
 *
 *
 *  Physical internal memory on DM6446     Memory partitioning in this .tcf
 *
 *              |//////////|                           |//////////|
 *  0x11800000  +----------+               0x11800000  +----------+
 *              | L2Cache  |                           |          |
 *              |  and/or  | 64k                       | L2 Cache | 64k
 *              |  IRAM    |                           |          |
 *              |          |                           |          |
 *  0x11810000  +----------+               0x11810000  +----------+
 *              |//////////|                           |//////////|
 *              :          :                           :          :
 *              |//////////|                           |//////////|
 *  0x11F04000  +----------+               0x11F04000  +----------+
 *              |          |                           |          |
 *              | L1DSRAM  | 48k                       | L1DSRAM  | 48k 
 *              |          |                           |          |     
 *  0x11F10000  +- - - - - +               0x11F10000  +- - - - - +     
 *              |L1Cache or| 32k                       | L1Cache  | 32k 
 *              |more L1DSR|                           |          |     
 *  0x11F18000  +----------+               0x11F18000  +----------+     
 *              |//////////|                           |//////////|
 */


/*
 *  Specify the L2 CACHE memory setting. This value indicates how the physical
 *  internal memory of size 64K starting at 0x11800000 will be split between
 *  L2 cache and a general-purpose internal memory segment IRAM. The options
 *  are:
 *  l2Mode: "0k"  -- IRAM is 64K long, starts at 0x11800000; no L2 cache
 *  l2Mode: "32k" -- IRAM is 32K long, starts at 0x11800000; L2 cache is
 *                           32K long, starts at 0x11808000
 *  l2Mode: "64k" -- no IRAM; L2 cache is 64k long, starts at 0x11800000
 */
var device_regs = {
    l1DMode: platformParams[platform].l1DMode,
    l2Mode: "64k" 
};

var params = {
    clockRate: platformParams[platform].clockRate,
    catalogName: "ti.catalog.c6000",
    deviceName: platformParams[platform].deviceName,
    regs: device_regs,
    mem: mem_ext
};


utils.loadPlatform("ti.platforms.generic", params);

utils.getProgObjs(prog, bios);

// on DM6437, reset timer at startup
if (platformParams[platform].deviceName == "DM6437") {
    bios.CLK.RESETTIMER = true;
}

/*
 * Enable common BIOS features used by all examples
 */
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);

/*
 *  Enable heaps in the L1DSRAM (internal L1 cache ram, fixed size)
 *  and define the label for heap usage (usually for DMAN3); make
 *  the heap as big as the entire segment
 */
bios.L1DSRAM.createHeap       = true;
bios.L1DSRAM.enableHeapLabel  = true;
bios.L1DSRAM["heapLabel"]     = prog.extern("L1DHEAP");
bios.L1DSRAM.heapSize         = platformParams[platform].l1dHeapSize;