io_map.h

DSP中使用PWM模块对电机进行控制

  #define TMRA1_COMSCR                  *((volatile word *)0x0000F05A)


  word Reserved0[5];                   /* Reserved (unused) registers */

} TMRA1_PRPH;

/******************************************
*** Peripheral TMRA2
*******************************************/
typedef volatile struct {
  /*** TMRA2_CMP1 - Timer A Channel 2 Compare Register #1; 0x0000F060 ***/
  union {
    word Word;
  } TMRA2_CMP1_STR;
  
  #define TMRA2_CMP1_COMPARISON_10_MASK 1U
  #define TMRA2_CMP1_COMPARISON_11_MASK 2U
  #define TMRA2_CMP1_COMPARISON_12_MASK 4U
  #define TMRA2_CMP1_COMPARISON_13_MASK 8U
  #define TMRA2_CMP1_COMPARISON_14_MASK 16U
  #define TMRA2_CMP1_COMPARISON_15_MASK 32U
  #define TMRA2_CMP1_COMPARISON_16_MASK 64U
  #define TMRA2_CMP1_COMPARISON_17_MASK 128U
  #define TMRA2_CMP1_COMPARISON_18_MASK 256U
  #define TMRA2_CMP1_COMPARISON_19_MASK 512U
  #define TMRA2_CMP1_COMPARISON_110_MASK 1024U
  #define TMRA2_CMP1_COMPARISON_111_MASK 2048U
  #define TMRA2_CMP1_COMPARISON_112_MASK 4096U
  #define TMRA2_CMP1_COMPARISON_113_MASK 8192U
  #define TMRA2_CMP1_COMPARISON_114_MASK 16384U
  #define TMRA2_CMP1_COMPARISON_115_MASK 32768U
  #define TMRA2_CMP1_COMPARISON__10_MASK 1023U
  #define TMRA2_CMP1_COMPARISON__10_BITNUM 0U
  #define TMRA2_CMP1_COMPARISON_1_10_MASK 64512U
  #define TMRA2_CMP1_COMPARISON_1_10_BITNUM 10U
  #define TMRA2_CMP1                    *((volatile word *)0x0000F060)


  /*** TMRA2_CMP2 - Timer A Channel 2 Compare Register #2; 0x0000F061 ***/
  union {
    word Word;
  } TMRA2_CMP2_STR;
  
  #define TMRA2_CMP2_COMPARISON_20_MASK 1U
  #define TMRA2_CMP2_COMPARISON_21_MASK 2U
  #define TMRA2_CMP2_COMPARISON_22_MASK 4U
  #define TMRA2_CMP2_COMPARISON_23_MASK 8U
  #define TMRA2_CMP2_COMPARISON_24_MASK 16U
  #define TMRA2_CMP2_COMPARISON_25_MASK 32U
  #define TMRA2_CMP2_COMPARISON_26_MASK 64U
  #define TMRA2_CMP2_COMPARISON_27_MASK 128U
  #define TMRA2_CMP2_COMPARISON_28_MASK 256U
  #define TMRA2_CMP2_COMPARISON_29_MASK 512U
  #define TMRA2_CMP2_COMPARISON_210_MASK 1024U
  #define TMRA2_CMP2_COMPARISON_211_MASK 2048U
  #define TMRA2_CMP2_COMPARISON_212_MASK 4096U
  #define TMRA2_CMP2_COMPARISON_213_MASK 8192U
  #define TMRA2_CMP2_COMPARISON_214_MASK 16384U
  #define TMRA2_CMP2_COMPARISON_215_MASK 32768U
  #define TMRA2_CMP2_COMPARISON__20_MASK 1023U
  #define TMRA2_CMP2_COMPARISON__20_BITNUM 0U
  #define TMRA2_CMP2_COMPARISON_2_10_MASK 64512U
  #define TMRA2_CMP2_COMPARISON_2_10_BITNUM 10U
  #define TMRA2_CMP2                    *((volatile word *)0x0000F061)


  /*** TMRA2_CAP - Timer A Channel 2 Capture Register; 0x0000F062 ***/
  union {
    word Word;
  } TMRA2_CAP_STR;
  
  #define TMRA2_CAP                     *((volatile word *)0x0000F062)


  /*** TMRA2_LOAD - Timer A Channel 2 Load Register; 0x0000F063 ***/
  union {
    word Word;
  } TMRA2_LOAD_STR;
  
  #define TMRA2_LOAD_LOAD0_MASK         1U
  #define TMRA2_LOAD_LOAD1_MASK         2U
  #define TMRA2_LOAD_LOAD2_MASK         4U
  #define TMRA2_LOAD_LOAD3_MASK         8U
  #define TMRA2_LOAD_LOAD4_MASK         16U
  #define TMRA2_LOAD_LOAD5_MASK         32U
  #define TMRA2_LOAD_LOAD6_MASK         64U
  #define TMRA2_LOAD_LOAD7_MASK         128U
  #define TMRA2_LOAD_LOAD8_MASK         256U
  #define TMRA2_LOAD_LOAD9_MASK         512U
  #define TMRA2_LOAD_LOAD10_MASK        1024U
  #define TMRA2_LOAD_LOAD11_MASK        2048U
  #define TMRA2_LOAD_LOAD12_MASK        4096U
  #define TMRA2_LOAD_LOAD13_MASK        8192U
  #define TMRA2_LOAD_LOAD14_MASK        16384U
  #define TMRA2_LOAD_LOAD15_MASK        32768U
  #define TMRA2_LOAD                    *((volatile word *)0x0000F063)


  /*** TMRA2_HOLD - Timer A Channel 2 Hold Register; 0x0000F064 ***/
  union {
    word Word;
  } TMRA2_HOLD_STR;
  
  #define TMRA2_HOLD_HOLD0_MASK         1U
  #define TMRA2_HOLD_HOLD1_MASK         2U
  #define TMRA2_HOLD_HOLD2_MASK         4U
  #define TMRA2_HOLD_HOLD3_MASK         8U
  #define TMRA2_HOLD_HOLD4_MASK         16U
  #define TMRA2_HOLD_HOLD5_MASK         32U
  #define TMRA2_HOLD_HOLD6_MASK         64U
  #define TMRA2_HOLD_HOLD7_MASK         128U
  #define TMRA2_HOLD_HOLD8_MASK         256U
  #define TMRA2_HOLD_HOLD9_MASK         512U
  #define TMRA2_HOLD_HOLD10_MASK        1024U
  #define TMRA2_HOLD_HOLD11_MASK        2048U
  #define TMRA2_HOLD_HOLD12_MASK        4096U
  #define TMRA2_HOLD_HOLD13_MASK        8192U
  #define TMRA2_HOLD_HOLD14_MASK        16384U
  #define TMRA2_HOLD_HOLD15_MASK        32768U
  #define TMRA2_HOLD                    *((volatile word *)0x0000F064)


  /*** TMRA2_CNTR - Timer A Channel 2 Counter Register; 0x0000F065 ***/
  union {
    word Word;
  } TMRA2_CNTR_STR;
  
  #define TMRA2_CNTR                    *((volatile word *)0x0000F065)


  /*** TMRA2_CTRL - Timer A Channel 2 Control Register; 0x0000F066 ***/
  union {
    word Word;
  } TMRA2_CTRL_STR;
  
  #define TMRA2_CTRL_OM0_MASK           1U
  #define TMRA2_CTRL_OM1_MASK           2U
  #define TMRA2_CTRL_OM2_MASK           4U
  #define TMRA2_CTRL_Co_INIT_MASK       8U
  #define TMRA2_CTRL_DIR_MASK           16U
  #define TMRA2_CTRL_LENGTH_MASK        32U
  #define TMRA2_CTRL_ONCE_MASK          64U
  #define TMRA2_CTRL_SCS0_MASK          128U
  #define TMRA2_CTRL_SCS1_MASK          256U
  #define TMRA2_CTRL_PCS0_MASK          512U
  #define TMRA2_CTRL_PCS1_MASK          1024U
  #define TMRA2_CTRL_PCS2_MASK          2048U
  #define TMRA2_CTRL_PCS3_MASK          4096U
  #define TMRA2_CTRL_CM0_MASK           8192U
  #define TMRA2_CTRL_CM1_MASK           16384U
  #define TMRA2_CTRL_CM2_MASK           32768U
  #define TMRA2_CTRL_OM_MASK            7U
  #define TMRA2_CTRL_OM_BITNUM          0U
  #define TMRA2_CTRL_SCS_MASK           384U
  #define TMRA2_CTRL_SCS_BITNUM         7U
  #define TMRA2_CTRL_PCS_MASK           7680U
  #define TMRA2_CTRL_PCS_BITNUM         9U
  #define TMRA2_CTRL_CM_MASK            57344U
  #define TMRA2_CTRL_CM_BITNUM          13U
  #define TMRA2_CTRL                    *((volatile word *)0x0000F066)


  /*** TMRA2_SCR - Timer A Channel 2 Status and Control Register; 0x0000F067 ***/
  union {
    word Word;
  } TMRA2_SCR_STR;
  
  #define TMRA2_SCR_OEN_MASK            1U
  #define TMRA2_SCR_OPS_MASK            2U
  #define TMRA2_SCR_FORCE_MASK          4U
  #define TMRA2_SCR_VAL_MASK            8U
  #define TMRA2_SCR_EEOF_MASK           16U
  #define TMRA2_SCR_MSTR_MASK           32U
  #define TMRA2_SCR_Capture_Mode0_MASK  64U
  #define TMRA2_SCR_Capture_Mode1_MASK  128U
  #define TMRA2_SCR_INPUT_MASK          256U
  #define TMRA2_SCR_IPS_MASK            512U
  #define TMRA2_SCR_IEFIE_MASK          1024U
  #define TMRA2_SCR_IEF_MASK            2048U
  #define TMRA2_SCR_TOFIE_MASK          4096U
  #define TMRA2_SCR_TOF_MASK            8192U
  #define TMRA2_SCR_TCFIE_MASK          16384U
  #define TMRA2_SCR_TCF_MASK            32768U
  #define TMRA2_SCR_Capture_Mode_MASK   192U
  #define TMRA2_SCR_Capture_Mode_BITNUM 6U
  #define TMRA2_SCR                     *((volatile word *)0x0000F067)


  /*** TMRA2_CMPLD1 - Timer A Channel 2 Comparator Load Register 1; 0x0000F068 ***/
  union {
    word Word;
  } TMRA2_CMPLD1_STR;
  
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_10_MASK 1U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_11_MASK 2U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_12_MASK 4U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_13_MASK 8U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_14_MASK 16U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_15_MASK 32U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_16_MASK 64U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_17_MASK 128U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_18_MASK 256U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_19_MASK 512U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_110_MASK 1024U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_111_MASK 2048U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_112_MASK 4096U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_113_MASK 8192U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_114_MASK 16384U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_115_MASK 32768U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD__10_MASK 1023U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD__10_BITNUM 0U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_1_10_MASK 64512U
  #define TMRA2_CMPLD1_COMPARATOR_LOAD_1_10_BITNUM 10U
  #define TMRA2_CMPLD1                  *((volatile word *)0x0000F068)


  /*** TMRA2_CMPLD2 - Timer A Channel 2 Comparator Load Register 2; 0x0000F069 ***/
  union {
    word Word;
  } TMRA2_CMPLD2_STR;
  
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_20_MASK 1U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_21_MASK 2U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_22_MASK 4U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_23_MASK 8U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_24_MASK 16U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_25_MASK 32U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_26_MASK 64U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_27_MASK 128U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_28_MASK 256U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_29_MASK 512U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_210_MASK 1024U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_211_MASK 2048U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_212_MASK 4096U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_213_MASK 8192U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_214_MASK 16384U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_215_MASK 32768U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD__20_MASK 1023U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD__20_BITNUM 0U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_2_10_MASK 64512U
  #define TMRA2_CMPLD2_COMPARATOR_LOAD_2_10_BITNUM 10U
  #define TMRA2_CMPLD2                  *((volatile word *)0x0000F069)


  /*** TMRA2_COMSCR - Timer A Channel 2 Comparator Status and Control Register; 0x0000F06A ***/
  union {
    word Word;
  } TMRA2_COMSCR_STR;
  
  #define TMRA2_COMSCR_CL10_MASK        1U
  #define TMRA2_COMSCR_CL11_MASK        2U
  #define TMRA2_COMSCR_CL20_MASK        4U
  #define TMRA2_COMSCR_CL21_MASK        8U
  #define TMRA2_COMSCR_TCF1_MASK        16U
  #define TMRA2_COMSCR_TCF2_MASK        32U
  #define TMRA2_COMSCR_TCF1EN_MASK      64U
  #define TMRA2_COMSCR_TCF2EN_MASK      128U
  #define TMRA2_COMSCR_CL_10_MASK       3U
  #define TMRA2_COMSCR_CL_10_BITNUM     0U
  #define TMRA2_COMSCR_CL_20_MASK       12U
  #define TMRA2_COMSCR_CL_20_BITNUM     2U
  #define TMRA2_COMSCR_TCF_1_MASK       48U
  #define TMRA2_COMSCR_TCF_1_BITNUM     4U
  #define TMRA2_COMSCR                  *((volatile word *)0x0000F06A)


  word Reserved0[5];                   /* Reserved (unused) registers */

} TMRA2_PRPH;

/******************************************
*** Peripheral TMRA3
*******************************************/
typedef volatile struct {
  /*** TMRA3_CMP1 - Timer A Channel 3 Compare Register #1; 0x0000F070 ***/
  union {
    word Word;
  } TMRA3_CMP1_STR;
  
  #define TMRA3_CMP1_COMPARISON_10_MASK 1U
  #define TMRA3_CMP1_COMPARISON_11_MASK 2U
  #define TMRA3_CMP1_COMPARISON_12_MASK 4U
  #define TMRA3_CMP1_COMPARISON_13_MASK 8U
  #define TMRA3_CMP1_COMPARISON_14_MASK 16U
  #define TMRA3_CMP1_COMPARISON_15_MASK 32U
  #define TMRA3_CMP1_COMPARISON_16_MASK 64U
  #define TMRA3_CMP1_COMPARISON_17_MASK 128U
  #define TMRA3_CMP1_COMPARISON_18_MASK 256U
  #define TMRA3_CMP1_COMPARISON_19_MASK 512U
  #define TMRA3_CMP1_COMPARISON_110_MASK 1024U
  #define TMRA3_CMP1_COMPARISON_111_MASK 2048U
  #define TMRA3_CMP1_COMPARISON_112_MASK 4096U
  #define TMRA3_CMP1_COMPARISON_113_MASK 8192U
  #define TMRA3_CMP1_COMPARISON_114_MASK 16384U
  #define TMRA3_CMP1_COMPARISON_115_MASK 32768U
  #define TMRA3_CMP1_COMPARISON__10_MASK 1023U
  #define TMRA3_CMP1_COMPARISON__10_BITNUM 0U
  #define TMRA3_CMP1_COMPARISON_1_10_MASK 64512U
  #define TMRA3_CMP1_COMPARISON_1_10_BITNUM 10U
  #define TMRA3_CMP1                    *((volatile word *)0x0000F070)


  /*** TMRA3_CMP2 - Timer A Channel 3 Compare Register #2; 0x0000F071 ***/
  union {
    word Word;
  } TMRA3_CMP2_STR;
  
  #define TMRA3_CMP2_COMPARISON_20_MASK 1U
  #define TMRA3_CMP2_COMPARISON_21_MASK 2U
  #define TMRA3_CMP2_COMPARISON_22_MASK 4U
  #define TMRA3_CMP2_COMPARISON_23_MASK 8U
  #define TMRA3_CMP2_COMPARISON_24_MASK 16U
  #define TMRA3_CMP2_COMPARISON_25_MASK 32U
  #define TMRA3_CMP2_COMPARISON_26_MASK 64U
  #define TMRA3_CMP2_COMPARISON_27_MASK 128U
  #define TMRA3_CMP2_COMPARISON_28_MASK 256U
  #define TMRA3_CMP2_COMPARISON_29_MASK 512U
  #define TMRA3_CMP2_COMPARISON_210_MASK 1024U
  #define TMRA3_CMP2_COMPARISON_211_MASK 2048U
  #define TMRA3_CMP2_COMPARISON_212_MASK 4096U
  #define TMRA3_CMP2_COMPARISON_213_MASK 8192U
  #define TMRA3_CMP2_COMPARISON_214_MASK 16384U
  #define TMRA3_CMP2_COMPARISON_215_MASK 32768U
  #define TMRA3_CMP2_COMPARISON__20_MASK 1023U
  #defi