fwxsc1.s

来自「PXA255 WINCE 4.2 BSP ,该BSP是商用的。」· S 代码 · 共 830 行 · 第 1/2 页

    INCLUDE kxarm.h
    INCLUDE oalintra.inc
    INCLUDE XSC1.inc
    INCLUDE XSC1bd.inc
    INCLUDE fwXsc1.inc    
;    INCLUDE sa11x1.inc

EBOOT_PARTITION_PHY_BASE        EQU     SDRAM_PHY_EBOOT_PARTITION
EBOOT_PARTITION_VIR_C_BASE      EQU     SDRAM_VIR_C_EBOOT_PARTITION


CLOCK_200MHz EQU 0x100
CLOCK_300MHz EQU 0x180
CLOCK_400MHz EQU 0x200

CLOCK_CPU_SPEED EQU CLOCK_200MHz	; set core clock to 200/300/400 MHz
CLOCK_CPU_TURBO	EQU	0		; 0/1 switch to turbo mode clock

GPIO_GPSR0_VAL EQU 0xffffffff  ; GPIO pin output set registers
GPIO_GPSR1_VAL EQU 0xffffffff
GPIO_GPSR2_VAL EQU 0xffffffff

GPIO_GPCR0_VAL EQU 0x08022080  ; GPIO pin output clear registers
GPIO_GPCR1_VAL EQU 0x00000000
GPIO_GPCR2_VAL EQU 0x00000000

GPIO_GPDR0_VAL EQU 0xc00220d8  ; GPIO pin direction registers
GPIO_GPDR1_VAL EQU 0xfcffab82
GPIO_GPDR2_VAL EQU 0x0000ffff

GPIO_GAFR0_L_VAL EQU 0x00000000  ; GPIO alternate function registers
GPIO_GAFR0_U_VAL EQU 0xa5000010
GPIO_GAFR1_L_VAL EQU 0x599a9550
GPIO_GAFR1_U_VAL EQU 0xaaa5aaaa
GPIO_GAFR2_L_VAL EQU 0xaaaaaaaa
GPIO_GAFR2_U_VAL EQU 0x00000000

MEM_MSC0_VAL EQU 0x2ef15af0		; static memory controller
MEM_MSC1_VAL EQU 0x32cc32cc
MEM_MSC2_VAL EQU 0x3ff43ff4

PCMCIA_MECR_VAL EQU 0x00000000	; pcmcia memory controller
PCMCIA_MCMEM0_VAL EQU 0x00010504
PCMCIA_MCMEM1_VAL EQU 0x00010504
PCMCIA_MCATT0_VAL EQU 0x00010504
PCMCIA_MCATT1_VAL EQU 0x00010504
PCMCIA_MCIO0_VAL EQU 0x00004715
PCMCIA_MCIO1_VAL EQU 0x00004715

	OPT   1

	IF :LNOT: :DEF: ETHBOOT     ; see eboot\fwp2.s
		IMPORT KernelStart
	ELSE
		IMPORT main
	ENDIF

	STARTUPTEXT
	LEAF_ENTRY StartUp

	; exception table should be at address 0x0
reset
	b reset_handler
undef_inst
	b undef_inst		; undefined instruction
soft_int
	b soft_int			; software interupt
pfetch_abort
	b pfetch_abort		; abort prefetch
data_abort
	b data_abort		; abort data
not_used
	b not_used			; not used
irq_int
	b irq_int			; interupt request IRQ
fiq_int
	b fiq_int			; fast interupt request FIQ


	LTORG ; time-critical path
    ALIGN 32

UART_CTRL_BASE EQU 0x40100000

putc_ttys0
	ldr r1, =(UART_CTRL_BASE+0x14)
	ldr r1, [r1]
	tst r1, #0x40
	beq putc_ttys0

	and r1, r0, #0xff
	ldr r0, =UART_CTRL_BASE
	str r1, [r0]
	mov pc, lr

	; initialize SDRAM memory controler

MEMORY_CTRL_MDCNFG EQU 0x00
MEMORY_CTRL_MDREFR EQU 0x04
MEMORY_CTRL_MDMRS EQU 0x40

SLF_REFRESH EQU 0x400000
HALF_MEMCLK EQU 0x0a4000
MEMCLK_RUN EQU 0x52000
MEMCLK_ENABLE EQU 0x9000

	; r0 = memory size, r1 = memory ctrl base

sdram_init
	ldr     r2, =(0x3800000 | SLF_REFRESH)
	ldr	r3, =0x0fff

	orr	r3, r3, r2
	str     r3, [r1, #MEMORY_CTRL_MDREFR]

	cmp	r0, #0x2000000
	orrgt	r2, r2, #0x30	; 64MB SDRAM
	orrle	r2, r2, #0x60	; 32MB SDRAM

	str     r2, [r1, #MEMORY_CTRL_MDREFR]	; set data refresh rate

	orr     r2, r2, #MEMCLK_RUN
	str     r2, [r1, #MEMORY_CTRL_MDREFR]	; set memclk free running

	bic	r2, r2, #SLF_REFRESH
	str     r2, [r1, #MEMORY_CTRL_MDREFR]   ; clear self refresh

	orr	r2, r2, #MEMCLK_ENABLE
	str     r2, [r1, #MEMORY_CTRL_MDREFR]   ; enable memclk

PART_ENABLE EQU 0x3

ROWADDR_12b EQU 0x20	; 32MB SDRAM on board
ROWADDR_13b EQU 0x40	; 64MB SDRAM on board

CAS2_RAS5_RC8 EQU 0x100	; 50MHz memclk
CAS3_RAS7_RC10 EQU 0x200	; 100MHz memclk
CAS3_RAS7_RC11 EQU 0x300

SA1111_MODE EQU 0x1000	; necessary for 64MB mode

	ldr	r2, =(0x888 | CAS3_RAS7_RC10)

	cmp     r0, #0x2000000
	orrgt   r2, r2, #ROWADDR_13b	 ; 64MB SDRAM
	orrgt   r2, r2, #SA1111_MODE
	orrle	r2, r2, #ROWADDR_12b	 ; 32MB SDRAM

	str     r2, [r1, #MEMORY_CTRL_MDCNFG]

	mov	r3, #0x400	; delay to wait for memory
delay
	nop
	nop
	subs	r3, r3, #1
	bne	delay
	nop
	nop
	nop

	orr	r2, r2, #PART_ENABLE
	str     r2, [r1, #MEMORY_CTRL_MDCNFG]

	ldr	r2, =0x220022
	str     r2, [r1, #MEMORY_CTRL_MDMRS]

	mov     pc, lr

try2wakeup		; if good sleep database, only  returns if special case

	; do checksum on the sleepdata

    ldr     r3, =(SLEEPDATA_BASE_PHYSICAL)
    ldr     r0, =(SLEEP_CHECKSUM_SEED)
    ldr     r2, =(SLEEPDATA_SIZE-1)
32
    ldr     r1, [r3], #4
    add     r0, r0, r1
    mov     r0, r0, ROR #31
    subs    r2, r2, #1
    bne     %b32
    
    ; checksum in r0, compare to cpsr

    ldr     r2, =PSPR_BASE_PHYSICAL
    ldr     r1, [r2]

    cmp     r0, r1
    bne     bad_checksum

    ldr    r3, =(SLEEPDATA_BASE_PHYSICAL+SleepState_SLEEP_TYPE)
    ldr    r1, [r3]
    cmp    r1, #SLEEP_TYPE_SOFT_RESET
    beq    soft_reset 

	; restore from sleep

    ldr r3, =(SLEEPDATA_BASE_PHYSICAL)

    ldr	r11, [r3, #SleepState_MMU_DOMAIN]   ; load the MMU domain access info
    ldr r9,  [r3, #SleepState_MMU_TTB]      ; load the MMU TTB info 
    ldr r8,  [r3, #SleepState_MMU_CTL]      ; load the MMU control info 
    ldr r7,  [r3, #SleepState_MMU_AUXCTL ]  ; 
    ldr r6,  [r3, #SleepState_PID ] ; 
    ldr r5,  [r3, #SleepState_AwakeAddr ]   ; load the lr address
    nop         
    nop
    nop
    nop
    nop

    mcr p15, 0, r11, c3, c0, 0      ; setup access to domain 0
    mcr p15, 0, r9,  c2, c0, 0      ; TTB address
    mcr p15, 0, r0,  c8, c7, 0      ; Invalidate I+D TLBs
    mcr p15, 0, r8,  c1, c0, 0      ; restore MMU control
    mcr p15, 0, r7,  c1, c1, 0      ; restore MMU Aux control
    mcr p15, 0, r6, c13, c0, 0      ; restore PID

    mov pc, r5		; jump to new virtual address

soft_reset
    orr    r10, r10, #RCSR_GPIO_RESET
    mov    r1, #0
    str    r1, [r3]

bad_checksum

    bic r10, r10, #RCSR_SLEEP_RESET
	mov  pc, lr

reset_handler

	ldr	r0, =0x2001
	mcr	p15,0,r0,c15,c1,0	; allow access to all coprocesors
	nop
	nop
	nop

	mov	r0, #0x78
	mcr	p15,0,r0,c1,c0,0	; disable MMU, caches, write buffer
	nop
	nop
	nop

	mov	r0, #0
	mcr	p15,0,r0,c8,c7,0	; flush v4 TLB
	mcr	p15,0,r0,c7,c7,0	; flush v3/v4 caches
	mcr	p15,0,r0,c7,c10,4	; flush write buffer
	nop
	nop
	nop

	mvn	r0, #0
	mcr	p15,0,r0,c3,c0,0	; grant access to all domains

	; read and init reset cause bits

	ldr     r0,  =RCSR_BASE_PHYSICAL
	ldr     r10, [r0]

	; extract the reset cause bits
	;
	mov     r2,  #RCSR_ALL
	and     r10,  r10,  r2		; r10 holds the conditioned reset reason

	; clear the reset cause bits
	str     r2,  [r0]

	; read and store pssr
	ldr     r0,  =PSSR_BASE_PHYSICAL
	ldr     r12, [r0]

	; extract the reset cause bits
	mov     r2,  #PSSR_VALID_MASK
	and     r12,  r12,  r2
	mov     r12,  r12,  lsl #16
	orr     r10,  r10,  r12			; r10 now has rcsr in lower half and pssr in upper

	; initialize GPIO registers

GPIO_BASE EQU 0x40e00000
GPIO_GPDR0 EQU 0x0c
GPIO_GPSR0 EQU 0x18
GPIO_GPCR0 EQU 0x24
GPIO_GAFR0_L EQU 0x54

	ldr	r0, =(GPIO_BASE | GPIO_GPSR0)
	ldr	r1, =GPIO_GPSR0_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPSR1_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPSR2_VAL
	str	r1, [r0]

	ldr	r0, =(GPIO_BASE | GPIO_GPCR0)
	ldr	r1, =GPIO_GPCR0_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPCR1_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPCR2_VAL
	str	r1, [r0]

	ldr	r0, =(GPIO_BASE | GPIO_GPDR0)
	ldr	r1, =GPIO_GPDR0_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPDR1_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GPDR2_VAL
	str	r1, [r0]

	ldr	r0, =(GPIO_BASE | GPIO_GAFR0_L)
	ldr	r1, =GPIO_GAFR0_L_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GAFR0_U_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GAFR1_L_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GAFR1_U_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GAFR2_L_VAL
	str	r1, [r0],#4
	ldr	r1, =GPIO_GAFR2_U_VAL
	str	r1, [r0]

PWR_CTRL_BASE EQU 0x40f00000
PWR_CTRL_PSSR EQU 0x4
PWR_PSSR_VAL EQU 0x30

	ldr     r2, =(PWR_CTRL_BASE | PWR_CTRL_PSSR)
	ldr     r3, =PWR_PSSR_VAL
	str     r3, [r2]

	; initialize pxa250 interupt controler

INTERUPT_CTRL_BASE EQU 0x40d00000
INTERUPT_CTRL_ICMR EQU 0x04

	ldr	r1, =(INTERUPT_CTRL_BASE | INTERUPT_CTRL_ICMR)
	mov	r2, #0
	str	r2, [r1]

    IF :LNOT: :DEF: ETHBOOT
    IF _FLASH != "1"
        b initperif
    ENDIF
    ENDIF

	; change core clock frequency

CLOCK_BASE EQU 0x41300000
CLOCK_CCCR EQU 0x0
CLOCK_CKEN EQU 0x4

	ldr	r1, =CLOCK_BASE

	mov	r2, #0
	str	r2, [r1, #CLOCK_CKEN]	; disable clocks

	mov	r2, #0x41
	orr	r2, r2, #CLOCK_CPU_SPEED	; set core clock (L:27,M:2)
	str	r2, [r1, #CLOCK_CCCR]

	mov	r1, #(0x2 | CLOCK_CPU_TURBO)
	mcr	p14,0,r1,c6,c0,0	; enter frequency change sequence


	; initialize pxa250 memory controler

MEMORY_CTRL_BASE EQU 0x48000000

	ldr     r1, =MEMORY_CTRL_BASE

	; initialize static memory controler

	ldr	r2, =MEM_MSC0_VAL
	str	r2, [r1, #MSC0_OFFSET]
	ldr	r2, [r1, #MSC0_OFFSET]

	ldr	r2, =MEM_MSC1_VAL
	str	r2, [r1, #MSC1_OFFSET]
	ldr	r2, [r1, #MSC1_OFFSET]

	ldr	r2, =MEM_MSC2_VAL
	str	r2, [r1, #MSC2_OFFSET]
	ldr	r2, [r1, #MSC2_OFFSET]

	; initialize pcmcia memory controler

	ldr     r2, =PCMCIA_MECR_VAL
	str     r2, [r1, #MECR_OFFSET]

	ldr     r2, =PCMCIA_MCMEM0_VAL
	str     r2, [r1, #MCMEM0_OFFSET]

	ldr     r2, =PCMCIA_MCMEM1_VAL
	str     r2, [r1, #MCMEM1_OFFSET]

	ldr     r2, =PCMCIA_MCATT0_VAL
	str     r2, [r1, #MCATT0_OFFSET]

	ldr     r2, =PCMCIA_MCATT1_VAL
	str     r2, [r1, #MCATT1_OFFSET]

	ldr     r2, =PCMCIA_MCIO0_VAL
	str     r2, [r1, #MCIO0_OFFSET]

	ldr     r2, =PCMCIA_MCIO1_VAL
	str     r2, [r1, #MCIO1_OFFSET]

	; initialize SDRAM memory controler

	ldr	r0, =0x4000000	; init SDRAM as 64MB
	bl	sdram_init