pmgrxsc1.s

PXA255 WINCE 4.2 BSP ,该BSP是商用的。

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; For preliminary module testing with no actual suspend / resume, uncomment the TEST_STUB_PWR_OFF definition below.
;
;      TITLE("XSC1 Firmware Initialization")
;++
;
; Copyright (c) 1999, 2002  Intel Corporation
;
; $Modtime: $
;--

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;   NOTES
;;
;; Mini-data cache not supported by Windows* CE yet, so not handled here.
;;
;;   End NOTES
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


    OPT     2                               ; disable listing

    INCLUDE kxarm.h
    INCLUDE XSC1.inc
    INCLUDE XSC1BD.inc
    INCLUDE fwXsc1.inc
    INCLUDE sa11x1.inc

;    IF PLAT_LUBBOCK = "1"
;    INCLUDE lubbock.mac
;    ENDIF

    IF :DEF: USING_COPROCSUPPORT
    IMPORT XSC1SetCP0Acc
    IMPORT XSC1GetCP0Acc
    ENDIF    ;Endif of USING_COPROCSUPPORT

    IMPORT OsSpecificDebugCommsResume    
    ;OPT     128                            ; disable listing of macro expansions
    OPT     1                               ; reenable listing

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;   Debug and development optional assembly switches

    
;TEST_STUB_PWR_OFF       EQU 1               ; Before real content
;TEST_SHOW_LEDS          EQU 1
DOING_SLEEP_MEDIATED_SOFT_RESET   EQU 1
TEST_WAKE_SKIP_GP0      EQU 1
;TEST_WAKE_SKIP_RTC      EQU 1
;TEST_SHOW_CKSM          EQU 1
;TEST_SHOW_CKEN          EQU 1

;TEST_FORCING_GPIO1_WAKEUP       EQU 1
;TEST_LED_DISPLAY         
;TEST_LED_DISPLAY_FORCE_SHORT    EQU 1
;TEST_INCLUDE_THIS_ANYWAY       EQU 1
;TEST_NOT_REALLY_SLEEPING    EQU 1
  IF !:DEF: TEST_SR_AUTO_REPEAT   
    ; Testing.  Wake up in n seconds.  Forces RTC wakeup enabled (normal).
;TEST_SR_AUTO_REPEAT    EQU 1 ;
  ENDIF; :DEF :TEST_SR_AUTO_REPEAT   
  IF :DEF: TEST_SR_AUTO_REPEAT   
    IF !:DEF: TEST_SHOW_LEDS
TEST_SHOW_LEDS          EQU 1
    ENDIF ; :NOT: :DEF: TEST_SHOW_LEDS 
  ENDIF; :DEF :TEST_SR_AUTO_REPEAT   

REAL_RESTORING_CP0_AND_14    EQU 1

REAL_NOT_ONLY_REG_SAVE_RSTR    EQU 1

  IF :DEF: REAL_NOT_ONLY_REG_SAVE_RSTR
    ; Don't define any of these if just testing register save / restore

;TEST_CLEARING_RTC_INTS         EQU 1
REAL_RESTORING_GPIOS           EQU 1
REAL_RESTORING_OST    EQU 1

REAL_RESTORING_ICMR    EQU 1
  IF :DEF: REAL_RESTORING_ICMR
TEST_MASK_OFF_ALL_ICMR         EQU 1
  ENDIF; :DEF: REAL_RESTORING_ICMR

REAL_RESTORING_FPGA            EQU 1
  IF :DEF: REAL_RESTORING_FPGA
    ; Don't shut it down unless you're going to restore it!
TEST_SHUTTING_DOWN_FPGA     EQU 1
  ENDIF; :DEF: REAL_RESTORING_FPGA

  ENDIF; :DEF: REAL_NOT_ONLY_REG_SAVE_RSTR

REAL_FLUSH_DATA_CACHE       EQU 1

    ; For SLEEP MEDIATED SOFT RESET
RTC_WAKEUP_DELAY_SECONDS_SOFT_RST    EQU 1  ; as fast as possible.  Don't change
    ; For sleep repeat test
    ; Long enough for operator to turn off switch without getting caught in sleep 
    ;   because  of short retrigger latency after wakeup.
RTC_WAKEUP_DELAY_SECONDS_REP_TEST    EQU 3  

;DEBUGPRINT_SLEEPDELAY_CNT   EQU 0x10000000


;;  Local definitions.  Should move to xsc1.inc and maybe follow a new naming convention.

; Register bit definitions
RTC_AL              EQU 0x00000001 
RTC_HZ              EQU 0x00000002

PWER_GPIO_BITS      EQU 0x0000FFFF  ; GPIOs 0..15 are possible wakeup sources.

    IF B_STEP_PXA2X0 = "1"
                                        ; Pin positions 81..95 are reserved.
GPIOREG2_RESERVED_AND_MASK  EQU 0x0001FFFF  ;  and must be set to 0.
                                       ; For the GAFRs, the reserved bits are
GAFR2_H_RESERVED_AND_MASK   EQU 0x00000003  ;  GAFR2_H (only two not reserved)

    ELSE ; IF B_STEP_PXA2X0 = "1"
                                        ; Pin positions 90..95 are reserved.
GPIOREG2_RESERVED_AND_MASK  EQU 0x03FFFFFF  ;  and must be set to 0.
                                       ; For the GAFRs, the reserved bits are
GAFR2_H_RESERVED_AND_MASK   EQU 0x000FFFFF  ;  GAFR2_H (12 bits not reserved)

    ENDIF ; ELSE of IF B_STEP_PXA2X0 = "1"

; PCFR definitions
PMGR_PCFR_VAL     EQU   PCFR_OPDE  ; When sleeping: Disable 32MHz osc, force PCMCIA and nCS lines

; PWER definitions
PMGR_PWER_WERTC EQU  0x80000000 ; Bit 31, enables RTC wakeup


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Interesting PGSRn definitions in platform context


;; GPIO lines to be forced high (memory chip selects and PCMCIA negative enables):
;; All others forced low to save power

;MMCCS0 is an active low signal in one MMC mode (SPI)
;nCS[1..5] are static chip selects under the control of the PGSR.
;nCS[0] is the boot memory chip select.  It is not under PGSR control.
;No other memory chip selects are under the control of the PGSR.
;
;nSDCS (SDRAM chip selects) and nCSx
;
; MBGNT/GP[13] GPIO pin level must be set to '0.'  Setting it high can
;  cause failure to wake if an alternate bus master is connected.  There is
;  ambiguity on this in the developer's manual; experience indicates that it
;  must be held low during sleep.
;
; Bit definitions for PGSRs: same as GPIOs, actually.

;   PGSR0: 0 .. 31
PGSR_MMCCS0     EQU 0x00000100  ; pin  8: bit  8  Active low and floats in sleep
PGSR_nCS1       EQU 0x00008000  ; pin 15: bit 15
PGSR_TOKEYPAD   EQU 0x00000008  ; pin 3

;   PGSR1  32 .. 63
PGSR_nCS5       EQU 0x00000002  ; pin 33: bit 1
PGSR_FF_nDTR    EQU 0x00000100      ; pin 40: bit 8
PGSR_FF_nRTS    EQU 0x00000200      ; pin 41: bit 9
PGSR_BT_nRTS    EQU (0x1 :SHL: 13)  ; pin 45: bit 13


PGSR_nPOE       EQU 0x00010000  ; pin 48: bit 16
PGSR_nPWE       EQU 0x00020000  ; pin 49: bit 17
PGSR_nPIOR      EQU 0x00040000  ; pin 50: bit 18
PGSR_nPIOW      EQU 0x00080000  ; pin 51: bit 19
PGSR_nPCE1      EQU 0x00100000  ; pin 52: bit 20
PGSR_nPCE2      EQU 0x00200000  ; pin 53 bit  21
PGSR_nP_MASK    EQU 0x003F0000  ; all PCMCIA-GPIO bits

;   PGSR2 64 .. 80
PGSR_nCS2       EQU 0x00004000  ; pin 78: bit 14
PGSR_nCS3       EQU 0x00008000  ; pin 79: bit 15
PGSR_nCS4       EQU 0x00010000  ; pin 80: bit 16

;   All others cleared in PGSRs.


;    IF PLAT_LUBBOCK = "1"
    ; In XSC1BD, all nCSx are either actually or potentially connected and
    ;   so should be set high (deselecting target devices) during sleep.
    ; Also disable all controllable PCMCIA lines (active low)
    ;  and MMCCS0 (active low).  MMCCS1 is not connected in Lubbock and is
    ;  initialized as an output, so it doesn't need special handling.

PMGR_PGSR0_SET_MASK EQU (PGSR_MMCCS0:OR:PGSR_nCS1)
PMGR_PGSR1_SET_MASK EQU (PGSR_nCS5:OR:PGSR_FF_nDTR:OR:PGSR_FF_nRTS:OR:PGSR_BT_nRTS:OR:PGSR_nP_MASK)
PMGR_PGSR2_SET_MASK EQU (PGSR_nCS2:OR:PGSR_nCS3:OR:PGSR_nCS4)
;    ENDIF

    IF PLAT_SANDGATE = "1"
; @@@ TBD
;   PMGR_PGSR0_SET_MASK EQU (PGSR_nCS1)
;   PMGR_PGSR1_SET_MASK EQU (PGSR_nCS5)
;   PMGR_PGSR2_SET_MASK EQU (PGSR_nCS2:OR:PGSR_nCS3:OR:PGSR_nCS4)

    ENDIF

;
;PCFR:  FS AND FP ARE SET TO ZERO, MEANING FORCED TO PGSR VALUE, NOT FLOATED
;        DS = 0    (No Deep Sleep)
;        OPDE = 1 (Stop 3 MHz oscillator during sleep):  Assume RTC driven off 32K osc.
;

;; Set wakeup  conditions.

PMGR_PXER_GPIO2_BIT  EQU  (0x1 :SHL: 2)
PMGR_PXER_KPDIN_BIT  EQU  (PMGR_PXER_GPIO2_BIT)
PMGR_PXER_GPIO4_BIT  EQU  (0x1 :SHL: 4)
PMGR_PXER_GPIO5_BIT  EQU  (0x1 :SHL: 5)

    IF PLAT_LUBBOCK = "1"
    ; In XSC1BD, wake up only for GPIO1 (S12) or GPIO0 (S13 or UCB1400 touch interrupt)
    ;   For this platform, GPIO 0 is falling edge triggered, 1 is rising edge triggered. 

    ; Rising edge wakeup triggers
PMGR_PRER_BITS  EQU  0x0002 ; GPIO 1 wakes on rising edge

    ; Falling edge wakeup triggers

    IF :DEF: TEST_WAKE_SKIP_GP0
PMGR_PFER_BITS_X  EQU  0x0000 ; Skip GPIO 0 wakes on falling edge
    ELSE ; TEST_WAKE_SKIP_GP0
PMGR_PFER_BITS_X  EQU  0x0001 ; GPIO 0 wakes on falling edge
    ENDIF ; TEST_WAKE_SKIP_GP0

    IF :DEF: USING_KEYPAD
    ; For Lubbock only, optional keypad triggers wakeup on GPIO 2 if present: falling edge
PMGR_PFER_BITS  EQU  (PMGR_PFER_BITS_X:OR:PMGR_PXER_KPDIN_BIT)
    ELSE  ; IF :DEF: USING_KEYPAD
PMGR_PFER_BITS  EQU  PMGR_PFER_BITS_X 
    ENDIF ; ELSE of IF:DEF: USING_KEYPAD


    ENDIF ; PLAT_LUBBOCK


    IF PLAT_SANDGATE = "1"

    ; Rising edge wakeup triggers
PMGR_PRER_BITS  EQU  0x0002 ; GPIO 1 wakes on rising edge

    ; Falling edge wakeup triggers
PMGR_PFER_BITS  EQU  0x0000 ; Not using any falling edge triggers

    ENDIF; PLAT_SANDGATE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;
;;
;;  Some hex display macros
;;

;; 
;;   Note: restricted to this macro because MS ARM assembler
;;      can't deal with the ldr r0, =($parameter) construct in
;;      a macro definition.
;; 

;;    R1 is undefined

    MACRO
    VIRT_HEX_DISP_REG_NOT_R1  $dispReg, $delay

;    IF :DEF: PLAT_LUBBOCK
;    IF :DEF: TEST_LED_DISPLAY
;
;        ldr     r1,  =(FPGA_REGS_BASE_U_VIRTUAL)
;        str     $dispReg,  [r1, #HEXLED_OFFSET]
;    IF :DEF: TEST_LED_DISPLAY_FORCE_SHORT
;        mov     r1, #0x10
;    ELSE
;        ldr     r1, =($delay)
;    ENDIF ; TEST_LED_DISPLAY_FORCE_SHORT
;11
;        subs    r1, r1, #1
;        bne     %B11
;
;    ENDIF; :DEF: TEST_LED_DISPLAY
;    ENDIF; :DEF: PLAT_LUBBOCK

    MEND

;; End of macro defs
;;;;;;;;;;;;;;


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


    TEXTAREA

    IF :DEF: PLAT_LUBBOCK
;; Debug support for Lubbock only, with MMU enabled.


    LEAF_ENTRY WriteHexLeds


;      ldr     r1,  =(FPGA_REGS_BASE_U_VIRTUAL)
;      str     r0,  [r1, #HEXLED_OFFSET]

      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF


    LEAF_ENTRY GetHexLeds


;      ldr     r1,  =(FPGA_REGS_BASE_U_VIRTUAL)
;      ldr     r0,  [r1, #HEXLED_OFFSET]

      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF

    ENDIF; :DEF: PLAT_LUBBOCK


;
; XSC1GetSPSR - Returns the Saved Program Status Register
;
; This routine is called byby the IRQ interrupt handler when
; PMU is active and capturing data
;
;       Entry   Interrupts disabled
;       Exit    Interrupts disabled
;       Uses    r0 returns SPSR

    LEAF_ENTRY XSC1GetSPSR

    mrs     r0, SPSR
      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF

;; End of XSC1GetSPSR()
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;
; CPUEnterIdle - system idle
;
; NOTE: Implementation of OEMIdle moved to OEMIdle.c
;
; This routine is called by OEMIdle in order to enter IDLE mode
;
;
;       Entry   Interrupts disabled
;       Exit    none
;       Uses    r0,r1,r2
;

    LEAF_ENTRY CPUEnterIdle

	; Get APD bit
	; If not set, set it to save power during idle        ;
    ldr     r1,  =MEMC_BASE_U_VIRTUAL		; we're in virt. mode
    ldr     r2,  [r1, #MDREFR_OFFSET]		; r2 contents of mdrefr

	; set the APD bit
	;
	orr		r0,	 r2, #MDREFR_APD			
    ; write back to mdrefr
    ;
	str		r0,  [r1, #MDREFR_OFFSET]

        
	ldr     r0, =0x01                       ; 1 = Idle Mode 
    mcr     p14, 0, r0, c7, c0, 0           ; Enter Idle mode
	; Restore mdrefr's original setting
    ;
    str     r2,  [r1, #MDREFR_OFFSET]

      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF
 
;; End of CPUEnterIdle()
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;;;;;;;;;;;;;;;;;;;;;;;;;
;;  PwrMgrGetSleepDataCksm subroutine

    LEAF_ENTRY PwrMgrGetSleepDataCksm
;  Virtual addressing assumed.  (Can't use in pre-MMU startup without a change)
;  chksum returns in R0
;  Also uses R1,2,3
;  Assumes return address in link register