sfr_r82b.inc

基于7758的三相多功能电能表的设计程序

pwm2_trcmr		.btequ		3,trcmr		; PWM2 mode select bit
bfc_trcmr		.btequ		4,trcmr		; TRCGRC register function selection bit
bfd_trcmr		.btequ		5,trcmr		; TRCGRD register function selection bit
tstart_trcmr	.btequ		7,trcmr		; TRC count start bit
;
;-------------------------------------------------------
;   Timer RC control register 1
;-------------------------------------------------------
trccr1			.equ		0121h
toa_trccr1		.btequ		0,trccr1	; TRCIOA output level select bit
tob_trccr1		.btequ		1,trccr1	; TRCIOB output level select bit
toc_trccr1		.btequ		2,trccr1	; TRCIOC output level select bit
tod_trccr1		.btequ		3,trccr1	; TRCIOD output level select bit
tck0_trccr1		.btequ		4,trccr1	; Count source selection bit
tck1_trccr1		.btequ		5,trccr1	; Count source selection bit
tck2_trccr1		.btequ		6,trccr1	; Count source selection bit
cclr_trccr1		.btequ		7,trccr1	; TRC counter clear select bit
;
;-------------------------------------------------------
;   Timer RC interrupt enable register
;-------------------------------------------------------
trcier			.equ		0122h
imiea_trcier	.btequ		0,trcier	; Input capture / compare match interrupt enable bit A
imieb_trcier	.btequ		1,trcier	; Input capture / compare match interrupt enable bit B
imiec_trcier	.btequ		2,trcier	; Input capture / compare match interrupt enable bit C
imied_trcier	.btequ		3,trcier	; Input capture / compare match interrupt enable bit D
ovie_trcier		.btequ		7,trcier	; Overflow / underflow interrupt enable bit
;
;-------------------------------------------------------
;   Timer RC status register
;-------------------------------------------------------
trcsr			.equ		0123h
imfa_trcsr		.btequ		0,trcsr		; Input capture / compare match flag A
imfb_trcsr		.btequ		1,trcsr		; Input capture / compare match flag B
imfc_trcsr		.btequ		2,trcsr		; Input capture / compare match flag C
imfd_trcsr		.btequ		3,trcsr		; Input capture / compare match flag D
ovf_trcsr		.btequ		7,trcsr		; Overflow flag
;
;-------------------------------------------------------
;   Timer RC I/O contorol register 0
;-------------------------------------------------------
trcior0			.equ		0124h
ioa0_trcior0	.btequ		0,trcior0	; TRCGRA control bit
ioa1_trcior0	.btequ		1,trcior0	; TRCGRA control bit
ioa2_trcior0	.btequ		2,trcior0	; TRCGRA mode selection bit
iob0_trcior0	.btequ		4,trcior0	; TRCGRB control bit
iob1_trcior0	.btequ		5,trcior0	; TRCGRB control bit
iob2_trcior0	.btequ		6,trcior0	; TRCGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RC I/O contorol register 1
;-------------------------------------------------------
trcior1			.equ		0125h
ioc0_trcior1	.btequ		0,trcior1	; TRCGRC control bit
ioc1_trcior1	.btequ		1,trcior1	; TRCGRC control bit
ioc2_trcior1	.btequ		2,trcior1	; TRCGRC mode selection bit
iod0_trcior1	.btequ		4,trcior1	; TRCGRD control bit
iod1_trcior1	.btequ		5,trcior1	; TRCGRD control bit
iod2_trcior1	.btequ		6,trcior1	; TRCGRD mode selection bit
;
;-------------------------------------------------------
;   Timer RC Counter , Timer RC general register A,B,C,D
;-------------------------------------------------------
trc				.equ		0126h		; Timer RC counter
trcgra			.equ		0128h		; Timer RC general register A
trcgrb			.equ		012ah		; Timer RC general register B
trcgrc			.equ		012ch		; Timer RC general register C
trcgrd			.equ		012eh		; Timer RC general register D
;
;-------------------------------------------------------
;   Timer RC control register 2
;-------------------------------------------------------
trccr2			.equ		0130h
csel_trccr2		.btequ		5,trccr2	; Timer RC operating mode select bit
tceg0_trccr2	.btequ		6,trccr2	; TRCTRG input edge selection bit
tceg1_trccr2	.btequ		7,trccr2	; TRCTRG input edge selection bit
;
;-------------------------------------------------------
;   Timer RC digital filter function selection register
;-------------------------------------------------------
trcdf			.equ		0131h
dfa_trcdf		.btequ		0,trcdf		; TRCIOA pin digital filter function selection bit
dfb_trcdf		.btequ		1,trcdf		; TRCIOB pin digital filter function selection bit
dfc_trcdf		.btequ		2,trcdf		; TRCIOC pin digital filter function selection bit
dfd_trcdf		.btequ		3,trcdf		; TRCIOD pin digital filter function selection bit
dftrg_trcdf		.btequ		4,trcdf		; TRCTRG pin digital filter function selection bit
dfck0_trcdf		.btequ		6,trcdf		; Clock selection bit for digital filter function
dfck1_trcdf		.btequ		7,trcdf		; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RC output master enable register
;-------------------------------------------------------
trcoer			.equ		0132h
ea_trcoer		.btequ		0,trcoer	; TRCIOA output disable bit
eb_trcoer		.btequ		1,trcoer	; TRCIOB output disable bit
ec_trcoer		.btequ		2,trcoer	; TRCIOC output disable bit
ed_trcoer		.btequ		3,trcoer	; TRCIOD output disable bit
pto_trcoer		.btequ		7,trcoer	; INT0 of pulse output forced cutoff signal input enabled bit
;
;-------------------------------------------------------
;   Timer RD start register
;-------------------------------------------------------
trdstr			.equ		0137h
tstart0_trdstr	.btequ		0,trdstr	; TRD0 count start bit
tstart1_trdstr	.btequ		1,trdstr	; TRD1 count start bit
csel0_trdstr	.btequ		2,trdstr	; TRD0 count operation select bit
csel1_trdstr	.btequ		3,trdstr	; TRD1 count operation select bit
;
;-------------------------------------------------------
;   Timer RD mode register
;-------------------------------------------------------
trdmr			.equ		0138h
sync_trdmr		.btequ		0,trdmr		; Timer RD synchronous bit
bfc0_trdmr		.btequ		4,trdmr		; TRDGRC0 register function selection bit
bfd0_trdmr		.btequ		5,trdmr		; TRDGRD0 register function selection bit
bfc1_trdmr		.btequ		6,trdmr		; TRDGRC1 register function selection bit
bfd1_trdmr		.btequ		7,trdmr		; TRDGRD1 register function selection bit
;
;-------------------------------------------------------
;   Timer RD PWM mode register
;-------------------------------------------------------
trdpmr			.equ		0139h
pwmb0_trdpmr	.btequ		0,trdpmr	; PWM mode of TRDIOB0 selection bit
pwmc0_trdpmr	.btequ		1,trdpmr	; PWM mode of TRDIOC0 selection bit
pwmd0_trdpmr	.btequ		2,trdpmr	; PWM mode of TRDIOD0 selection bit
pwmb1_trdpmr	.btequ		4,trdpmr	; PWM mode of TRDIOB1 selection bit
pwmc1_trdpmr	.btequ		5,trdpmr	; PWM mode of TRDIOC1 selection bit
pwmd1_trdpmr	.btequ		6,trdpmr	; PWM mode of TRDIOD1 selection bit
;
;-------------------------------------------------------
;   Timer RD function control register
;-------------------------------------------------------
trdfcr			.equ		013ah
cmd0_trdfcr		.btequ		0,trdfcr	; Combination mode selection bit
cmd1_trdfcr		.btequ		1,trdfcr	; Combination mode selection bit
ols0_trdfcr		.btequ		2,trdfcr	; Normal-Phase output level selection bit
ols1_trdfcr		.btequ		3,trdfcr	; Counter-Phase output level selection bit
adtrg_trdfcr	.btequ		4,trdfcr	; A/D trigger enable bit
adeg_trdfcr		.btequ		5,trdfcr	; A/D trigger edge selection bit
stclk_trdfcr	.btequ		6,trdfcr	; External clock input selection bit
pwm3_trdfcr		.btequ		7,trdfcr	; PWM3 mode selection bit
;
;-------------------------------------------------------
;   Timer RD output master enable register 1
;-------------------------------------------------------
trdoer1			.equ		013bh
ea0_trdoer1		.btequ		0,trdoer1	; TRDIOA0 output disable bit
eb0_trdoer1		.btequ		1,trdoer1	; TRDIOB0 output disable bit
ec0_trdoer1		.btequ		2,trdoer1	; TRDIOC0 output disable bit
ed0_trdoer1		.btequ		3,trdoer1	; TRDIOD0 output disable bit
ea1_trdoer1		.btequ		4,trdoer1	; TRDIOA1 output disable bit
eb1_trdoer1		.btequ		5,trdoer1	; TRDIOB1 output disable bit
ec1_trdoer1		.btequ		6,trdoer1	; TRDIOC1 output disable bit
ed1_trdoer1		.btequ		7,trdoer1	; TRDIOD1 output disable bit
;
;-------------------------------------------------------
;   Timer RD output master enable register 2
;-------------------------------------------------------
trdoer2			.equ		013ch
pto_trdoer2		.btequ		7,trdoer2	; INT0 of pulse output forced cutoff signal input enabled bit
;
;-------------------------------------------------------
;   Timer RD output control register
;-------------------------------------------------------
trdocr			.equ		013dh
toa0_trdocr		.btequ		0,trdocr	; TRDIOA0 output level selection bit
tob0_trdocr		.btequ		1,trdocr	; TRDIOB0 output level selection bit
toc0_trdocr		.btequ		2,trdocr	; TRDIOC0 initial output level selection bit
tod0_trdocr		.btequ		3,trdocr	; TRDIOD0 initial output level selection bit
toa1_trdocr		.btequ		4,trdocr	; TRDIOA1 initial output level selection bit
tob1_trdocr		.btequ		5,trdocr	; TRDIOB1 initial output level selection bit
toc1_trdocr		.btequ		6,trdocr	; TRDIOC1 initial output level selection bit
tod1_trdocr		.btequ		7,trdocr	; TRDIOD1 initial output level selection bit
;
;-------------------------------------------------------
;   Timer RD digital filter function selection register 0
;-------------------------------------------------------
trddf0			.equ		013eh
dfa_trddf0		.btequ		0,trddf0	; TRDIOA pin digital filter function selection bit
dfb_trddf0		.btequ		1,trddf0	; TRDIOB pin digital filter function selection bit
dfc_trddf0		.btequ		2,trddf0	; TRDIOC pin digital filter function selection bit
dfd_trddf0		.btequ		3,trddf0	; TRDIOD pin digital filter function selection bit
dfck0_trddf0	.btequ		6,trddf0	; Clock selection bit for digital filter function
dfck1_trddf0	.btequ		7,trddf0	; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RD digital filter function selection register 1
;-------------------------------------------------------
trddf1			.equ		013fh
dfa_trddf1		.btequ		0,trddf1	; TRDIOA pin digital filter function selection bit
dfb_trddf1		.btequ		1,trddf1	; TRDIOB pin digital filter function selection bit
dfc_trddf1		.btequ		2,trddf1	; TRDIOC pin digital filter function selection bit
dfd_trddf1		.btequ		3,trddf1	; TRDIOD pin digital filter function selection bit
dfck0_trddf1	.btequ		6,trddf1	; Clock selection bit for digital filter function
dfck1_trddf1	.btequ		7,trddf1	; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RD control register 0
;-------------------------------------------------------
trdcr0			.equ		0140h
tck0_trdcr0		.btequ		0,trdcr0	; Count source selection bit
tck1_trdcr0		.btequ		1,trdcr0	; Count source selection bit
tck2_trdcr0		.btequ		2,trdcr0	; Count source selection bit
ckeg0_trdcr0	.btequ		3,trdcr0	; External clock edge selection bit
ckeg1_trdcr0	.btequ		4,trdcr0	; External clock edge selection bit
cclr0_trdcr0	.btequ		5,trdcr0	; TRD0 counter clear selection bit
cclr1_trdcr0	.btequ		6,trdcr0	; TRD0 counter clear selection bit
cclr2_trdcr0	.btequ		7,trdcr0	; TRD0 counter clear selection bit
;
;-------------------------------------------------------
;   Timer RD control register 1
;-------------------------------------------------------
trdcr1			.equ		0150h
tck0_trdcr1		.btequ		0,trdcr1	; Count source selection bit
tck1_trdcr1		.btequ		1,trdcr1	; Count source selection bit
tck2_trdcr1		.btequ		2,trdcr1	; Count source selection bit
ckeg0_trdcr1	.btequ		3,trdcr1	; External clock edge selection bit
ckeg1_trdcr1	.btequ		4,trdcr1	; External clock edge selection bit
cclr0_trdcr1	.btequ		5,trdcr1	; TRD1 counter clear selection bit
cclr1_trdcr1	.btequ		6,trdcr1	; TRD1 counter clear selection bit
cclr2_trdcr1	.btequ		7,trdcr1	; TRD1 counter clear selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register A0
;-------------------------------------------------------
trdiora0		.equ		0141h
ioa0_trdiora0	.btequ		0,trdiora0	; TRDGRA control bit
ioa1_trdiora0	.btequ		1,trdiora0	; TRDGRA control bit
ioa2_trdiora0	.btequ		2,trdiora0	; TRDGRA mode selection bit
ioa3_trdiora0	.btequ		3,trdiora0	; Input capture input switch bit
iob0_trdiora0	.btequ		4,trdiora0	; TRDGRB control bit
iob1_trdiora0	.btequ		5,trdiora0	; TRDGRB control bit
iob2_trdiora0	.btequ		6,trdiora0	; TRDGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register A1
;-------------------------------------------------------
trdiora1		.equ		0151h
ioa0_trdiora1	.btequ		0,trdiora1	; TRDGRA control bit
ioa1_trdiora1	.btequ		1,trdiora1	; TRDGRA control bit
ioa2_trdiora1	.btequ		2,trdiora1	; TRDGRA mode selection bit
ioa3_trdiora1	.btequ		3,trdiora1	; Input capture input switch bit
iob0_trdiora1	.btequ		4,trdiora1	; TRDGRB control bit
iob1_trdiora1	.btequ		5,trdiora1	; TRDGRB control bit
iob2_trdiora1	.btequ		6,trdiora1	; TRDGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register C0
;-------------------------------------------------------
trdiorc0		.equ		0142h
ioc0_trdiorc0	.btequ		0,trdiorc0	; TRDGRC control bit
ioc1_trdiorc0	.btequ		1,trdiorc0	; TRDGRC control bit
ioc2_trdiorc0	.btequ		2,trdiorc0	; TRDGRC mode selection bit
ioc3_trdiorc0	.btequ		3,trdiorc0	; TRDGRC register function selection bit
iod0_trdiorc0	.btequ		4,trdiorc0	; TRDGRD control bit
iod1_trdiorc0	.btequ		5,trdiorc0	; TRDGRD control bit
iod2_trdiorc0	.btequ		6,trdiorc0	; TRDGRD mode selection bit
iod3_trdiorc0	.btequ		7,trdiorc0	; TRDGRD register function selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register C1
;-------------------------------------------------------
trdiorc1		.equ		0152h
ioc0_trdiorc1	.btequ		0,trdiorc1	; TRDGRC control bit
ioc1_trdiorc1	.btequ		1,trdiorc1	; TRDGRC control bit
ioc2_trdiorc1	.btequ		2,trdiorc1	; TRDGRC mode selection bit
ioc3_trdiorc1	.btequ		3,trdiorc1	; TRDGRC register function selection bit
iod0_trdiorc1	.btequ		4,trdiorc1	; TRDGRD control bit
iod1_trdiorc1	.btequ		5,trdiorc1	; TRDGRD control bit
iod2_trdiorc1	.btequ		6,trdiorc1	; TRDGRD mode selection bit
iod3_trdiorc1	.btequ		7,trdiorc1	; TRDGRD register function selection bit
;
;-------------------------------------------------------
;   Timer RD status register 0
;-------------------------------------------------------
trdsr0			.equ		0143h
imfa_trdsr0		.btequ		0,trdsr0	; Input capture / compare match flag A
imfb_trdsr0		.btequ		1,trdsr0	; Input capture / compare match flag B
imfc_trdsr0		.btequ		2,trdsr0	; Input capture / compare match flag C
imfd_trdsr0		.btequ		3,trdsr0	; Input capture / compare match flag D
ovf_trdsr0		.btequ		4,trdsr0	; Overflow flag
;