sfr_r82b.inc

基于7758的三相多功能电能表的设计程序

;------------------------------------------------------------------------
;                                                                       |
;   FILE        :sfr_r82b.inc                                           |
;   DATE        :Tue, Dec 23, 2008                                      |
;   DESCRIPTION :define the sfr register. (for Assembler language)      |
;   CPU GROUP   :2A                                                     |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.4.12).     |
;                                                                       |
;------------------------------------------------------------------------

;************************************************************************************
;*																					*
;*  File Name   : SFR_R82B.inc														*
;*  Contents    : definition of R8C/2A & R8C/2B Group SFR							*
;*  Copyright(C) 2006. Renesas Technology Corp., All rights reserved.				*
;*  Version     : 1.20 (07-06-11)													*
;*                      correct & rename : 											*
;*                               u1irs_u2c1 to u2irs_u2c1							*
;*                               u1rrm_u2c1 to u2rrm_u2c1							*
;*                1.10 (06-12-27)													*
;*                     rename : trfc00_trfcr0 to tstart_trfcr0						*
;*                              trfc01_trfcr0 to tck0_trfcr0						*
;*                              trfc02_trfcr0 to tck1_trfcr0						*
;*                     correct & rename : 											*
;*                              trfc10_trfcr0 to tipf0_trfcr1						*
;*                              trfc11_trfcr0 to tipf1_trfcr1						*
;*                              trfc12_trfcr0 to cclr_trfcr1						*
;*                              trfc13_trfcr0 to tmod_trfcr1						*
;*                              trfc14_trfcr0 to trfc14_trfcr1						*
;*                              trfc15_trfcr0 to trfc15_trfcr1						*
;*                              trfc16_trfcr0 to trfc16_trfcr1						*
;*                              trfc17_trfcr0 to trfc17_trfcr1						*
;*                1.00 (06-10-03)													*
;*																					*
;*  note        :																	*
;*																					*
;************************************************************************************
;
;-------------------------------------------------------
;   Processor mode register0
;-------------------------------------------------------
pm0				.equ		0004h
pm03			.btequ		3,pm0		; Software reset bit
;
;-------------------------------------------------------
;   Processor mode register1
;-------------------------------------------------------
pm1				.equ		0005h
pm12			.btequ		2,pm1		; WDT interrupt/reset switch bit
;
;-------------------------------------------------------
;   System clock control register0
;-------------------------------------------------------
cm0				.equ		0006h
cm02			.btequ		2,cm0		; WAIT peripheral function clock stop bit
cm03			.btequ		3,cm0		; XCIN-XCOUT drive capacity select bit
cm04			.btequ		4,cm0		; Port XC Switch bit
cm05			.btequ		5,cm0		; Xin clock (Xin-Xout) stop bit
cm06			.btequ		6,cm0		; System clock division select bit0
cm07			.btequ		7,cm0		; CPU Clock Select bit
;
;-------------------------------------------------------
;   System clock control register1
;-------------------------------------------------------
cm1				.equ		0007h
cm10			.btequ		0,cm1		; All clock stop control bit
cm11			.btequ		1,cm1		; XIN-XOUT internal resistor select bit
cm12			.btequ		2,cm1		; XCIN-XCOUT internal resistor select bit
cm13			.btequ		3,cm1		; Port Xin-Xout switch bit
cm14			.btequ		4,cm1		; Low-speed on-chip oscillation stop bit
cm15			.btequ		5,cm1		; Xin-Xout drive capacity select bit
cm16			.btequ		6,cm1		; System clock division select bit1
cm17			.btequ		7,cm1		; System clock division select bit1
;
;-------------------------------------------------------
;   Module standby control register
;-------------------------------------------------------
mstcr			.equ		0008h
mstiic			.btequ		3,mstcr		; I2C Bus stanby bit 
msttrd			.btequ		4,mstcr		; Timer RD stanby bit
msttrc			.btequ		5,mstcr		; Timer RC stanby bit
;
;-------------------------------------------------------
;   Protect register
;-------------------------------------------------------
prcr			.equ		000ah
prc0			.btequ		0,prcr		; Protect bit0
prc1			.btequ		1,prcr		; Protect bit1
prc2			.btequ		2,prcr		; Protect bit2
prc3			.btequ		3,prcr		; Protect bit3
;
;-------------------------------------------------------
;   Oscillation stop detection register
;-------------------------------------------------------
ocd				.equ		000ch
ocd0			.btequ		0,ocd		; Oscillation stop detection enable bit
ocd1			.btequ		1,ocd		; Oscillation stop detection interrupt enable bit
ocd2			.btequ		2,ocd		; System clock select bit
ocd3			.btequ		3,ocd		; Clock monitor bit
;
;-------------------------------------------------------
;   Watchdog timer
;-------------------------------------------------------
wdtr			.equ		000dh		; Watchdog timer reset register
;
wdts			.equ		000eh		; Watchdog timer start register
;
wdc				.equ		000fh		; Watchdog timer control register
;
wdc7			.btequ		7,wdc		; Prescaler select bit
;
;-------------------------------------------------------
;   Address match interrupt enable register
;-------------------------------------------------------
aier			.equ		0013h
aier0			.btequ		0,aier		; Address match interrupt 0 enable bit
aier1			.btequ		1,aier		; Address match interrupt 1 enable bit
;
;-------------------------------------------------------
;   Count source protection mode register
;-------------------------------------------------------
cspr			.equ		001ch
cspro			.btequ		7,cspr		; Count source protection mode select bit
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 0
;-------------------------------------------------------
fra0			.equ		0023h
fra00			.btequ		0,fra0		; High-speed on-chip oscillator enable bit
fra01			.btequ		1,fra0		; High-speed on-chip oscillator select bit
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 1
;-------------------------------------------------------
fra1			.equ		0024h
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 2
;-------------------------------------------------------
fra2			.equ		0025h
fra20			.btequ		0,fra2		; High-speed on-chip oscillator frequency switching bit
fra21			.btequ		1,fra2		; High-speed on-chip oscillator frequency switching bit
fra22			.btequ		2,fra2		; High-speed on-chip oscillator frequency switching bit
;
;-------------------------------------------------------
;   Clock prescaler reset flag
;-------------------------------------------------------
cpsrf			.equ		0028h
cpsr			.btequ		7,cpsrf		; Clock prescaler reset flag
;
;-------------------------------------------------------
;   Voltage detection register 1
;-------------------------------------------------------
vca1			.equ		0031h
vca13			.btequ		3,vca1		; Voltage detection 2 signal monitor flag
;
;-------------------------------------------------------
;   Voltage detection register 2
;-------------------------------------------------------
vca2			.equ		0032h
vca20			.btequ		0,vca2		; Internal power low consumption enable bit
vca25			.btequ		5,vca2		; Voltage detection 0 enable bit
vca26			.btequ		6,vca2		; Voltage detection 1 enable bit
vca27			.btequ		7,vca2		; Voltage detection 2 enable bit
;
;-------------------------------------------------------
;   Voltage monitor 1 circuit control register
;-------------------------------------------------------
vw1c			.equ		0036h
vw1c0			.btequ		0,vw1c		; Voltage monitor 1 interrupt / reset enable bit
vw1c1			.btequ		1,vw1c		; Voltage monitor 1 digital filter disable mode select bit
vw1c2			.btequ		2,vw1c		; Voltage change detection flag
vw1c3			.btequ		3,vw1c		; Voltage detection 1 signal monitor flag
vw1f0			.btequ		4,vw1c		; Sampling clock select bit
vw1f1			.btequ		5,vw1c		; Sampling clock select bit
vw1c6			.btequ		6,vw1c		; Voltage monitor 1 circuit mode select bit
vw1c7			.btequ		7,vw1c		; Voltage monitor 1 interrupt / reset generation condition select bit
;
;-------------------------------------------------------
;   Voltage monitor 2 circuit control register
;-------------------------------------------------------
vw2c			.equ		0037h
vw2c0			.btequ		0,vw2c		; Voltage monitor 2 interrupt / reset enable bit
vw2c1			.btequ		1,vw2c		; Voltage monitor 2 digital filter disabled mode select bit
vw2c2			.btequ		2,vw2c		; Voltage change detection flag
vw2c3			.btequ		3,vw2c		; WDT Detection Flag
vw2f0			.btequ		4,vw2c		; Sampling clock select bit
vw2f1			.btequ		5,vw2c		; Sampling clock select bit
vw2c6			.btequ		6,vw2c		; Voltage monitor 2 circuit mode select bit
vw2c7			.btequ		7,vw2c		; Voltage monitor 2 interrupt / reset generation condition select bit
;
;-------------------------------------------------------
;   Voltage monitor 0 circuit control register
;-------------------------------------------------------
vw0c			.equ		0038h
vw0c0			.btequ		0,vw0c		; Voltage monitor 0 reset enable bit
vw0c1			.btequ		1,vw0c		; Voltage monitor 0 digital filter disabled mode select bit
vw0c2			.btequ		2,vw0c		; 
vw0f0			.btequ		4,vw0c		; Sampling clock select bit
vw0f1			.btequ		5,vw0c		; Sampling clock select bit
vw0c6			.btequ		6,vw0c		; Voltage monitor 0 circuit mode select bit
vw0c7			.btequ		7,vw0c		; Voltage monitor 0 reset generation condition select bit
;
;-------------------------------------------------------
;   UART0 bit rate register
;-------------------------------------------------------
u0brg			.equ		00a1h
;
;-------------------------------------------------------
;   UART1 bit rate register
;-------------------------------------------------------
u1brg			.equ		00a9h
;
;-------------------------------------------------------
;   UART2 bit rate register
;-------------------------------------------------------
u2brg			.equ		0161h
;
;-------------------------------------------------------
;   SS control register H
;-------------------------------------------------------
sscrh			.equ		00b8h
cks0_sscrh		.btequ		0,sscrh		; Transfer clock rate select bit
cks1_sscrh		.btequ		1,sscrh		; Transfer clock rate select bit
cks2_sscrh		.btequ		2,sscrh		; Transfer clock rate select bit
mss_sscrh		.btequ		5,sscrh		; Master/Slave device select bit
rsstp_sscrh		.btequ		6,sscrh		; Receive single stop bit
;
;-------------------------------------------------------
;   IIC bus control register 1
;-------------------------------------------------------
iccr1			.equ		00b8h
cks0_iccr1		.btequ		0,iccr1		; Transmit clock select bit 3 to 0
cks1_iccr1		.btequ		1,iccr1		; Transmit clock select bit 3 to 0
cks2_iccr1		.btequ		2,iccr1		; Transmit clock select bit 3 to 0
cks3_iccr1		.btequ		3,iccr1		; Transmit clock select bit 3 to 0
trs_iccr1		.btequ		4,iccr1		; Transfer/receive select bit
mst_iccr1		.btequ		5,iccr1		; Master/slave select bit
rcvd_iccr1		.btequ		6,iccr1		; Receive disable bit
ice_iccr1		.btequ		7,iccr1		; IIC bus interface enable bit
;
;-------------------------------------------------------
;   SS control register L
;-------------------------------------------------------
sscrl			.equ		00b9h
sres_sscrl		.btequ		1,sscrl		; Clock synchronous serial I/O with chip select control part reset bit
solp_sscrl		.btequ		4,sscrl		; SOL write protect bit
sol_sscrl		.btequ		5,sscrl		; Serial data output value setting bit
;
;-------------------------------------------------------
;   IIC bus control register 2
;-------------------------------------------------------
iccr2			.equ		00b9h
iicrst_iccr2	.btequ		1,iccr2		; IIC control part reset bit
sclo_iccr2		.btequ		3,iccr2		; SCL monitor flag
sdaop_iccr2		.btequ		4,iccr2		; SDAO write protect bit
sdao_iccr2		.btequ		5,iccr2		; SDA output value control bit
scp_iccr2		.btequ		6,iccr2		; Start/Stop condition generation disable bit
bbsy_iccr2		.btequ		7,iccr2		; Bus busy bit
;
;-------------------------------------------------------
;   SS mode register
;-------------------------------------------------------
ssmr			.equ		00bah
bc0_ssmr		.btequ		0,ssmr		; Bit counter 2 to 
bc1_ssmr		.btequ		1,ssmr		; Bit counter 2 to 
bc2_ssmr		.btequ		2,ssmr		; Bit counter 2 to 
cphs_ssmr		.btequ		5,ssmr		; SSCK clock phase select bit
cpos_ssmr		.btequ		6,ssmr		; SSCK clock polarity select bit
mls_ssmr		.btequ		7,ssmr		; MSB first/ LSB first select bit
;
;-------------------------------------------------------
;   IIC bus mode register
;-------------------------------------------------------
icmr			.equ		00bah
bc0_icmr		.btequ		0,icmr		; Bit counter 2 to 0
bc1_icmr		.btequ		1,icmr		; Bit Counter 2 to 0
bc2_icmr		.btequ		2,icmr		; Bit Counter 2 to 0
bcwp_icmr		.btequ		3,icmr		; BC write protect bit
wait_icmr		.btequ		6,icmr		; Wait insertion bit
mls_icmr		.btequ		7,icmr		; MSB-First/LSB-First select