frequency.tan.qmsg

这是一个通过外部按键来控制发光二极管发光的程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "frequency.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/frequency.vhd" 7 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "keydecoder:u3\|q5 " "Info: Detected ripple clock \"keydecoder:u3\|q5\" as buffer" {  } { { "keydecoder.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/keydecoder.vhd" 20 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "keydecoder:u3\|q5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keydecoder:u3\|q6 " "Info: Detected ripple clock \"keydecoder:u3\|q6\" as buffer" {  } { { "keydecoder.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/keydecoder.vhd" 20 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "keydecoder:u3\|q6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "keydecoder:u3\|keypressed " "Info: Detected gated clock \"keydecoder:u3\|keypressed\" as buffer" {  } { { "keydecoder.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/keydecoder.vhd" 18 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "keydecoder:u3\|keypressed" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp:u1\|clkout1 " "Info: Detected ripple clock \"fp:u1\|clkout1\" as buffer" {  } { { "fp.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fp.vhd" 31 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp:u1\|clkout1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register fptd:u4\|cnt4\[8\] register fptd:u4\|clkout4 70.42 MHz 14.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 70.42 MHz between source register \"fptd:u4\|cnt4\[8\]\" and destination register \"fptd:u4\|clkout4\" (period= 14.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.400 ns + Longest register register " "Info: + Longest register to register delay is 12.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fptd:u4\|cnt4\[8\] 1 REG LC1_B17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B17; Fanout = 4; REG Node = 'fptd:u4\|cnt4\[8\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "" { fptd:u4|cnt4[8] } "NODE_NAME" } "" } } { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.200 ns) 3.400 ns fptd:u4\|LessThan~1500 2 COMB LC2_B12 1 " "Info: 2: + IC(1.200 ns) + CELL(2.200 ns) = 3.400 ns; Loc. = LC2_B12; Fanout = 1; COMB Node = 'fptd:u4\|LessThan~1500'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "3.400 ns" { fptd:u4|cnt4[8] fptd:u4|LessThan~1500 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 6.000 ns fptd:u4\|LessThan~1551 3 COMB LC5_B13 1 " "Info: 3: + IC(1.100 ns) + CELL(1.500 ns) = 6.000 ns; Loc. = LC5_B13; Fanout = 1; COMB Node = 'fptd:u4\|LessThan~1551'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "2.600 ns" { fptd:u4|LessThan~1500 fptd:u4|LessThan~1551 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 7.900 ns fptd:u4\|LessThan~1509 4 COMB LC6_B13 1 " "Info: 4: + IC(0.000 ns) + CELL(1.900 ns) = 7.900 ns; Loc. = LC6_B13; Fanout = 1; COMB Node = 'fptd:u4\|LessThan~1509'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { fptd:u4|LessThan~1551 fptd:u4|LessThan~1509 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.000 ns) 12.400 ns fptd:u4\|clkout4 5 REG LC6_I19 1 " "Info: 5: + IC(3.500 ns) + CELL(1.000 ns) = 12.400 ns; Loc. = LC6_I19; Fanout = 1; REG Node = 'fptd:u4\|clkout4'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "4.500 ns" { fptd:u4|LessThan~1509 fptd:u4|clkout4 } "NODE_NAME" } "" } } { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 53.23 % ) " "Info: Total cell delay = 6.600 ns ( 53.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.800 ns ( 46.77 % ) " "Info: Total interconnect delay = 5.800 ns ( 46.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "12.400 ns" { fptd:u4|cnt4[8] fptd:u4|LessThan~1500 fptd:u4|LessThan~1551 fptd:u4|LessThan~1509 fptd:u4|clkout4 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.400 ns" { fptd:u4|cnt4[8] fptd:u4|LessThan~1500 fptd:u4|LessThan~1551 fptd:u4|LessThan~1509 fptd:u4|clkout4 } { 0.000ns 1.200ns 1.100ns 0.000ns 3.500ns } { 0.000ns 2.200ns 1.500ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 117 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 117; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/frequency.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns fptd:u4\|clkout4 2 REG LC6_I19 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_I19; Fanout = 1; REG Node = 'fptd:u4\|clkout4'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.400 ns" { clk fptd:u4|clkout4 } "NODE_NAME" } "" } } { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|clkout4 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|clkout4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 117 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 117; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/frequency.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns fptd:u4\|cnt4\[8\] 2 REG LC1_B17 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_B17; Fanout = 4; REG Node = 'fptd:u4\|cnt4\[8\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.400 ns" { clk fptd:u4|cnt4[8] } "NODE_NAME" } "" } } { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|cnt4[8] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|cnt4[8] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|clkout4 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|clkout4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|cnt4[8] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|cnt4[8] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "fptd.vhd" "" { Text "E:/课题软件程序/拨码开关＋二极管闪烁/fptd.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "12.400 ns" { fptd:u4|cnt4[8] fptd:u4|LessThan~1500 fptd:u4|LessThan~1551 fptd:u4|LessThan~1509 fptd:u4|clkout4 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.400 ns" { fptd:u4|cnt4[8] fptd:u4|LessThan~1500 fptd:u4|LessThan~1551 fptd:u4|LessThan~1509 fptd:u4|clkout4 } { 0.000ns 1.200ns 1.100ns 0.000ns 3.500ns } { 0.000ns 2.200ns 1.500ns 1.900ns 1.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|clkout4 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|clkout4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/课题软件程序/拨码开关＋二极管闪烁/db/frequency.quartus_db" { Floorplan "E:/课题软件程序/拨码开关＋二极管闪烁/" "" "1.900 ns" { clk fptd:u4|cnt4[8] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out fptd:u4|cnt4[8] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}