fptd.vhd

这是一个通过外部按键来控制发光二极管发光的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fptd is
  port(freq:in std_logic_vector(1 downto 0);
         en:in std_logic; 
       clk:in std_logic;   --系统时钟25M
       clkout:out std_logic);--用于驱动外部发光二极管的脉冲
end fptd;

architecture rtl of fptd is
  signal clkout1,clkout2,clkout3,clkout4:std_logic;
  signal cnt1:integer range 0 to 62500000;--0.4HZ
  signal cnt2:integer range 0 to 25000000;--1HZ
  signal cnt3:integer range 0 to 5000000;--5HZ
  signal cnt4:integer range 0 to 250000;--100HZ
begin

  process(en,freq)
   begin
    if(en='0')then
       clkout<='0';
    else
      case freq is
      when "00" =>clkout<=clkout1;--初始化时默认的输出频率为0.4HZ,周期为2.5s
      when "01" =>clkout<=clkout2;--1s
      when "10" =>clkout<=clkout3;--0.2s对应5HZ
      when "11" =>clkout<=clkout4;--0.01s
      when others=>
      end case;
    end if;
  end process;


  process(clk)
   begin
    if(clk'event and clk='1')then
        if(cnt1=62500000)then
           cnt1<=0;
        else
           cnt1<=cnt1+1;
        end if;
    end if;
  end process;
  process(clk,cnt1)
    begin
     if(clk'event and clk='1')then
        if(cnt1>=31250000)then
           clkout1<='1';
        else
           clkout1<='0';
        end if;
     end if;
  end process;



  process(clk)
   begin
    if(clk'event and clk='1')then
        if(cnt2=25000000)then
           cnt2<=0;
        else
           cnt2<=cnt2+1;
        end if;
    end if;
  end process;
  process(clk,cnt2)
    begin
     if(clk'event and clk='1')then
        if(cnt2>=12500000)then
           clkout2<='1';
        else
           clkout2<='0';
        end if;
     end if;
  end process;



  process(clk)
   begin
    if(clk'event and clk='1')then
        if(cnt3=5000000)then
           cnt3<=0;
        else
           cnt3<=cnt3+1;
        end if;
    end if;
  end process;
  process(clk,cnt3)
    begin
     if(clk'event and clk='1')then
        if(cnt3>=2500000)then
           clkout3<='1';
        else
           clkout3<='0';
        end if;
     end if;
  end process;



  process(clk)
   begin
    if(clk'event and clk='1')then
        if(cnt4=250000)then
           cnt4<=0;
        else
           cnt4<=cnt4+1;
        end if;
    end if;
  end process;
  process(clk,cnt4)
    begin
     if(clk'event and clk='1')then
        if(cnt4>=125000)then
           clkout4<='1';
        else
           clkout4<='0';
        end if;
     end if;
  end process;

end rtl;