asmfuncs.s

Next BIOS Source code : Extensible Firmware Interface

//++
// Copyright (c)  1999 - 2002 Intel Corporation. All rights reserved
// This software and associated documentation (if any) is furnished
// under a license and may only be used or copied in accordance
// with the terms of the license. Except as permitted by such
// license, no part of this software or documentation may be
// reproduced, stored in a retrieval system, or transmitted in any
// form or by any means without the express written consent of
// Intel Corporation.
//
//
// Module Name:
//
//  AsmFuncs.s
//
// Abstract:
//
//  Low level IPF routines used by the debug support driver
//
// Revision History:
//
//--


#include "common.i"
#include "Ds64Macros.i"

.global PatchSaveBuffer
.global IpfContextBuf
.global CommonHandler
.global ExternalInterruptCount


/////////////////////////////////////////////
//
//  Name:
//      InstructionCacheFlush
//
//  Description:
//      Flushes instruction cache for specified number of bytes
//
        .global InstructionCacheFlush
        .proc   InstructionCacheFlush
        .align 32
InstructionCacheFlush::
 {      .mii
        alloc   r3=2, 0, 0, 0
        cmp4.leu p0,p6=32, r33;;
        (p6)    mov r33=32;;
 }
 {      .mii
        nop.m    0
        zxt4    r29=r33;;
        dep.z   r30=r29, 0, 5;;
 }
 {      .mii
        cmp4.eq p0,p7=r0, r30
        shr.u   r28=r29, 5;;
        (p7)    adds    r28=1, r28;;
 }
 {      .mii
        nop.m    0
        shl r27=r28, 5;;
        zxt4    r26=r27;;
 }
 {      .mfb
        add r31=r26, r32
        nop.f    0
        nop.b    0
 }
LoopBack:   // $L143:
 {      .mii
        fc   r32
        adds    r32=32, r32;;
        cmp.ltu p14,p15=r32, r31
 }
 {      .mfb
        nop.m    0
        nop.f    0
        //(p14) br.cond.dptk.few $L143#;;
        (p14)   br.cond.dptk.few LoopBack;;
 }
 {      .mmi
        sync.i;;
        srlz.i
        nop.i   0;;
 }
 {      .mfb
        nop.m    0
        nop.f    0
        br.ret.sptk.few b0;;
 }
        .endp   InstructionCacheFlush


/////////////////////////////////////////////
//
//  Name:
//      ChainHandler
//
//  Description:
//      Chains an interrupt handler
//
//      The purpose of this function is to enable chaining of the external interrupt.
//      Since there's no clean SAL abstraction for doing this, we must do it
//      surreptitiously.
//
//      The reserved IVT entry at offset 0x3400 is coopted for use by this handler.
//      According to Itanium architecture, it is reserved.  Strictly speaking, this is
//      not safe, as we're cheating and violating the Itanium architecture.  However,
//      as long as we're the only ones cheating, we should be OK.  Without hooks in
//      the SAL to enable IVT management, there aren't many good options.
//
//      The strategy is to replace the first bundle of the external interrupt handler
//      with our own that will branch into a piece of code we've supplied and located
//      in the reserved IVT entry.  Only the first bundle of the external interrupt
//      IVT entry is modified.
//
//      The original bundle is moved and relocated to space
//      allocated within the reserved IVT entry.  The next bundle following is
//      is generated to go a hard coded branch back to the second bundle of the
//      external interrupt IVT entry just in case the first bundle had no branch.
//
//      Our new code will execute our handler, and then fall through to the
//      original bundle after restoring all context appropriately.
//
//      The following is a representation of what the IVT memory map looks like with
//      our chained handler installed:
//
//
//