📄 costas.mdl
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const "0"
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType Reference
Name "Compare\nTo Constant1"
Ports [1, 1]
Position [560, 535, 590, 565]
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Constant"
SourceType "Compare To Constant"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop ">="
const "0"
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType Reference
Name "Compare\nTo Zero"
Ports [1, 1]
Position [490, 335, 520, 365]
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Zero"
SourceType "Compare To Zero"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop ">="
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType Reference
Name "Compare\nTo Zero1"
Ports [1, 1]
Position [480, 445, 510, 475]
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Zero"
SourceType "Compare To Zero"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop ">="
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType ComplexToRealImag
Name "Complex to\nReal-Imag1"
Ports [1, 2]
Position [275, 68, 305, 97]
ShowName off
Output "Real and imag"
Port {
PortNumber 2
Name "Q"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Constant
Name "Constant1"
Position [765, 220, 795, 250]
ShowName off
Value "eps"
SampleTime "Tsym"
}
Block {
BlockType Constant
Name "Constant3"
Position [570, 300, 600, 330]
ShowName off
SampleTime "-1"
}
Block {
BlockType Constant
Name "Constant4"
Position [560, 480, 590, 510]
ShowName off
SampleTime "-1"
}
Block {
BlockType Constant
Name "Constant5"
Position [950, 465, 980, 495]
ShowName off
Value "pi/4*0"
SampleTime "-1"
}
Block {
BlockType DataTypeConversion
Name "Data Type \nConversion"
Position [610, 262, 650, 288]
ShowName off
OutDataTypeMode "double"
}
Block {
BlockType DataTypeConversion
Name "Data Type \nConversion1"
Position [545, 337, 560, 363]
ShowName off
OutDataTypeMode "double"
}
Block {
BlockType DataTypeConversion
Name "Data Type \nConversion2"
Position [530, 447, 545, 473]
ShowName off
OutDataTypeMode "double"
}
Block {
BlockType DataTypeConversion
Name "Data Type \nConversion3"
Position [615, 537, 630, 563]
ShowName off
OutDataTypeMode "double"
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [890, 172, 920, 203]
Inputs "*/"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [960, 176, 995, 204]
ShowName off
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain3"
Position [960, 396, 995, 424]
ShowName off
Gain "pi/4"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain4"
Position [580, 336, 615, 364]
ShowName off
Gain "2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain5"
Position [570, 446, 605, 474]
ShowName off
Gain "2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Isum2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [585, 117, 650, 133]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "1"
bwr "20"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Isum2"
nSgCpl "0"
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [1, 1]
Position [535, 110, 565, 140]
ShowName off
Operator "square"
}
Block {
BlockType Math
Name "Math\nFunction1"
Ports [1, 1]
Position [535, 80, 565, 110]
ShowName off
Operator "square"
}
Block {
BlockType Math
Name "Math\nFunction3"
Ports [1, 1]
Position [760, 180, 790, 210]
ShowName off
Operator "square"
}
Block {
BlockType Product
Name "Product1"
Ports [3, 1]
Position [825, 59, 850, 151]
ShowName off
Inputs "***"
CollapseMode "All dimensions"
InputSameDT off
RndMeth "Floor"
}
Block {
BlockType Product
Name "Product5"
Ports [3, 1]
Position [700, 436, 725, 504]
ShowName off
Inputs "***"
CollapseMode "All dimensions"
InputSameDT off
RndMeth "Floor"
}
Block {
BlockType Product
Name "Product6"
Ports [3, 1]
Position [705, 306, 730, 374]
ShowName off
Inputs "***"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "double"
RndMeth "Floor"
}
Block {
BlockType Reference
Name "Qsum2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [585, 87, 650, 103]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "1"
bwr "20"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Qsum2"
nSgCpl "0"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [710, 176, 730, 214]
ShowName off
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [680, 96, 700, 134]
ShowName off
Inputs "-+"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum3"
Ports [2, 1]
Position [840, 186, 860, 224]
ShowName off
Inputs "2"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum6"
Ports [2, 1]
Position [635, 321, 655, 359]
ShowName off
Inputs "-+"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum7"
Ports [2, 1]
Position [635, 451, 655, 489]
ShowName off
Inputs "+-"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum8"
Ports [2, 1]
Position [800, 391, 820, 429]
ShowName off
Inputs "+-"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum9"
Ports [2, 1]
Position [1030, 401, 1050, 439]
ShowName off
Inputs "2"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SampleTime "Tsym"
}
Block {
BlockType Reference
Name "sss"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [725, 107, 790, 123]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "1"
bwr "20"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sss"
nSgCpl "0"
}
Block {
BlockType Reference
Name "sss1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [875, 122, 940, 138]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "2"
bwr "40"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sss1"
nSgCpl "0"
}
Block {
BlockType Reference
Name "sss2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [1065, 122, 1130, 138]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "3"
bwr "29"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sss2"
nSgCpl "0"
}
Block {
BlockType Reference
Name "sss4"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [1070, 412, 1135, 428]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "3"
bwr "29"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sss4"
nSgCpl "0"
}
Block {
BlockType Reference
Name "sss5"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [860, 402, 925, 418]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Fractional"
nodetype "Input Port"
bwl "2"
bwr "10"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sss5"
nSgCpl "0"
}
Block {
BlockType Outport
Name "CarPD"
Position [1160, 123, 1190, 137]
IconDisplay "Port number"
BusOutputAsStru⌨️ 快捷键说明
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