interrupts.c

analog device vdsp dynamic power control tutorial

#include "..\BF561_Regulator.h"

/************************************************************************
 * PROGRAMMABLE FLAG A INTERRUPT HANDLER								*
 *																		*
 * Acknowledges the PFA (SW6-7) interrupt and modifies core regulator	*
 * voltage by decrementing the VLEV field of VR_CTL.  If VLEV is at the	*
 * minimum, it will do nothing.	 If decrementing VLEV results in a core	*
 * voltage under 1.0 V, the PLL_DIV register is written to lower the	*
 * CCLK to VC0/2 (to prevent overclocking of the core at low voltage).	*
 ************************************************************************/
EX_INTERRUPT_HANDLER(PFA_HANDLER)
{
	short VR_CTL_val, VLEV_field;

	*pFIO0_FLAG_C = 0x0060;				// Acknowledge PFA Interrupt

	*pSICB_SYSCR |= 0x0080;				// Raise Core B Supplemental-Int0

	VR_CTL_val = *pVR_CTL; 				// Read Current Value of VR_CTL
										// and dump VLEV field into VLEV_field
	VLEV_field = (VR_CTL_val & VLEV_MASK) >> 4;
	
	if(VLEV_field != 0x3)				// if VLEV > MIN (0x3)
	{
		if((--VLEV_field) == 0x8)		// Decrement VLEV
		{								// Check For Switch To Low Power (Vcc < 1V)
			*pPLL_DIV |= 0x10;			// CCLK = VCO/2 (Don't Overclock At Low Power)
			ssync();
		}
	}
	
	VR_CTL_val &= ~VLEV_MASK;			// ZERO out VLEV field
	VR_CTL_val |= (VLEV_field << 4);	// Dump VLEV into VLEV position within VR_CTL

	while(*pSICB_SYSCR & 0x0800);		// Wait: Core B Acknowledge SUP-B0	

	*pVR_CTL = VR_CTL_val;	
	idle();
	
	*pFIO2_FLAG_D &= 0xFF;				// Clear Upper LEDs First	
	*pFIO2_FLAG_D |= (VLEV_field << 8);	// Then Display New VLEV On LED5-8
}

/************************************************************************
 * PROGRAMMABLE FLAG B INTERRUPT HANDLER								*
 *																		*
 * Acknowledges the PFB (SW8-9) interrupt and modifies core regulator	*
 * voltage by incrementing the VLEV field of VR_CTL.  If VLEV is at the	*
 * maximum, it will wrap to the lowest level of 0.70 V.					*
 ************************************************************************/
EX_INTERRUPT_HANDLER(PFB_HANDLER)
{
	short VR_CTL_val, VLEV_field;

	*pFIO0_FLAG_C = 0x0180;				// Acknowledge PFB Interrupt

	*pSICB_SYSCR |= 0x0080;				// Raise Core B Supplemental-Int0

	VR_CTL_val = *pVR_CTL; 				// Read Current Value of VR_CTL
										// and dump VLEV field into VLEV_field
	VLEV_field = (VR_CTL_val & VLEV_MASK) >> 4;
		
	if(VLEV_field != 0xF)				// If VLEV < MAX (0xF), increment it
	{
		if((++VLEV_field) == 0x8)		// Otherwise increment VLEV
		{
			*pPLL_DIV &= 0x0F;			// Revert to default CCLK = VCO/1 once it is
			ssync();					// safe to do so...
		}
	}
		
	VR_CTL_val &= ~VLEV_MASK;			// ZERO out VLEV field
	VR_CTL_val |= (VLEV_field << 4);	// Dump VLEV into VLEV position within VR_CTL
	
	while(*pSICB_SYSCR & 0x0800);		// Wait: Core B Acknowledge SUP-B0

	*pVR_CTL = VR_CTL_val;	
	idle();
	
	*pFIO2_FLAG_D &= 0xFF;				// Clear Upper LEDs First	
	*pFIO2_FLAG_D |= (VLEV_field << 8);	// Then Display New VLEV On LED5-8
}