interrupts.c

analog device vdsp dynamic power control tutorial

#include "..\BF561_Regulator.h"

/************************************************************************
 * SUPPLEMENTAL INTERRUPT 0 HANDLER										*
 *																		*
 * Core B MUST be in idle when core A reprograms the on-chip regulator.	*
 * Core A will raise the supplemental interrupt 0 when it is about to	*
 * go into idle mode after writing to VR_CTL.  This ISR simply idles	*
 * Core B in preparation for the VR_CTL wake-up.						*
 ************************************************************************/
EX_INTERRUPT_HANDLER(SUP0_HANDLER)
{
	*pSICB_SYSCR = 0x0800;		// Acknowledge Supplemental Interrupt

	idle();						// IDLE for VR_CTL Write By Core A
}