branch prediction dual-core.ldf

analog device vdsp branch prediction tutorial

/* MANAGED-BY-SYSTEM-BUILDER                                    */

/*
** ADSP-BF561 linker description file generated on May 26, 2006 at 00:16:57.
**
** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by 
** changing the appropriate options rather than editing this file. 
**
** Configuration:-
**     crt_doj:                                .\Release\Branch Prediction Dual-Core_basiccrt.doj
**     processor:                              ADSP-BF561
**     si_revision:                            automatic
**     using_cplusplus:                        true
**     mem_init:                               false
**     use_vdk:                                false
**     use_eh:                                 true
**     use_argv:                               true
**     user_heap_src_file:                     C:\Build Tools\nightly_build\cvsStage\_4.5ExportBlackfinReGen\Examples\No Hardware Required\Compiler Features\Branch Prediction Dual-Core\Branch Prediction Dual-Core_heaptab.c
**     libraries_use_stdlib:                   true
**     libraries_use_fileio_libs:              false
**     libraries_use_ieeefp_emulation_libs:    false
**     libraries_use_eh_enabled_libs:          false
**     system_heap:                            L1
**     system_heap_min_size:                   2K
**     system_stack:                           L1
**     system_stack_min_size:                  2K
**     use_sdram:                              false
**     use_multicores:                         2
**     use_multicores_use_core:                multi_core
**
*/

ARCHITECTURE(ADSP-BF561)

SEARCH_DIR($ADI_DSP/Blackfin/lib)


// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## mty.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## mty.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj
      

#define LIBS \
   RT_LIB_NAME(mc561) \
   ,RT_LIB_NAME(small561) \
   ,RT_LIB_NAME_MT(io561) \
   ,RT_LIB_NAME_MT(c561) \
   ,RT_LIB_NAME_MT(event561) \
   ,RT_LIB_NAME_MT(x561) \
   ,RT_LIB_NAME_EH_MT(cpp561) \
   ,RT_LIB_NAME_EH_MT(cpprt561) \
   ,RT_LIB_NAME(f64ieee561) \
   ,RT_LIB_NAME(dsp561) \
   ,RT_LIB_NAME(sftflt561) \
   ,RT_LIB_NAME(etsi561) \
   ,RT_LIB_NAME(ssl561) \
   ,RT_LIB_NAME(drv561) \
   ,RT_LIB_NAME(rt_fileio561) \

$LIBS = LIBS;
$LIBRARIES_CORE_A = 

/*$VDSG<insert-user-libraries-coreA-beginning>                  */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-coreA-beginning>                  */

   corea.dlb
   ,$LIBS {(!DualCoreMem("CoreB")) && (!sharing("MustShare"))}

/*$VDSG<insert-user-libraries-coreA-end>                        */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-coreA-end>                        */

   ;

$LIBRARIES_CORE_B = 

/*$VDSG<insert-user-libraries-coreB-beginning>                  */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-coreB-beginning>                  */

   coreb.dlb
   ,$LIBS {(!DualCoreMem("CoreA")) && (!sharing("MustShare"))}

/*$VDSG<insert-user-libraries-coreB-end>                        */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-coreB-end>                        */

   ;

$LIBRARIES_SML2 = 

/*$VDSG<insert-user-libraries-shared-memory-L2-beginning>       */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared-memory-L2-beginning>       */

   sml2.dlb
   ,$LIBS

/*$VDSG<insert-user-libraries-shared-memory-L2-end>             */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared-memory-L2-end>             */

   ;

$LIBRARIES_SML3 = 

/*$VDSG<insert-user-libraries-shared-memory-L3-beginning>       */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared-memory-L3-beginning>       */

   sml3.dlb
   ,$LIBS

/*$VDSG<insert-user-libraries-shared-memory-L3-end>             */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared-memory-L3-end>             */

   ;

$LIBRARIES_SML2_CM = 
   $LIBRARIES_SML2

/*$VDSG<insert-user-libraries-common-memory-L2>                 */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-common-memory-L2>                 */

   ;

$LIBRARIES_SML3_CM = 
   $LIBRARIES_SML3

/*$VDSG<insert-user-libraries-common-memory-L3>                 */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-common-memory-L3>                 */

   ;

$LIBRARIES_SHARED = 
   $LIBS

/*$VDSG<insert-user-libraries-shared>                           */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared>                           */

   ;

$OBJECTS_CORE_A = 

/*$VDSG<insert-user-objects-for-coreA-beginning>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreA-beginning>                */

   ".\Release\Branch Prediction Dual-Core_basiccrt.doj"
   , RT_LIB_NAME(profile561)
   , $COMMAND_LINE_OBJECTS {!DualCoreMem("CoreB")}
   , "cplbtab561a.doj"
   , RT_OBJ_NAME(crtn561)

/*$VDSG<insert-user-objects-for-coreA-end>                      */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreA-end>                      */

   ;

$OBJS_LIBS_INTERNAL_CORE_A = 

/*$VDSG<insert-libraries-internal_coreA>                        */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreA>                        */

   $OBJECTS_CORE_A{prefersMem("internal")}, $LIBRARIES_CORE_A{prefersMem("internal")}

/*$VDSG<insert-libraries-internal_coreA-end>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreA-end>                    */

   ;

$OBJS_LIBS_NOT_EXTERNAL_CORE_A = 

/*$VDSG<insert-libraries-not-external_coreA>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreA>                    */

   $OBJECTS_CORE_A{!prefersMem("external")}, $LIBRARIES_CORE_A{!prefersMem("external")}

/*$VDSG<insert-libraries-not-external_coreA-end>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreA-end>                */

   ;

$OBJECTS_CORE_B = 

/*$VDSG<insert-user-objects-for-coreB-beginning>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreB-beginning>                */

   ".\Release\Branch Prediction Dual-Core_basiccrt.doj"
   , RT_LIB_NAME(profile561)
   , $COMMAND_LINE_OBJECTS {!DualCoreMem("CoreA")}
   , "cplbtab561b.doj"
   , RT_OBJ_NAME(crtn561)

/*$VDSG<insert-user-objects-for-coreB-end>                      */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreB-end>                      */

   ;

$OBJS_LIBS_INTERNAL_CORE_B = 

/*$VDSG<insert-libraries-internal_coreB>                        */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreB>                        */

   $OBJECTS_CORE_B{prefersMem("internal")}, $LIBRARIES_CORE_B{prefersMem("internal")}

/*$VDSG<insert-libraries-internal_coreB-end>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreB-end>                    */

   ;

$OBJS_LIBS_NOT_EXTERNAL_CORE_B = 

/*$VDSG<insert-libraries-not-external_coreB>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreB>                    */

   $OBJECTS_CORE_B{!prefersMem("external")}, $LIBRARIES_CORE_B{!prefersMem("external")}

/*$VDSG<insert-libraries-not-external_coreB-end>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreB-end>                */

   ;

$OBJECTS = $COMMAND_LINE_OBJECTS;

/*$VDSG<insert-user-macros>                                     */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros>                                     */


/*$VDSG<customise-async-macros>                                 */
/* This code is preserved if the LDF is re-generated.           */


#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM


/*$VDSG<customise-async-macros>                                 */


MEMORY
{
  /*
  ** ADSP-BF561 MEMORY MAP.
  **
  ** The known memory spaces are as follows:
  **
  ** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers
  ** 0xFFC00000 - 0xFFDFFFFF  System MMR (Shared)
  ** 0xFFB01000 - 0xFFBFFFFF    
  ** 0xFFB00000 - 0xFFB00FFF  Scratchpad  
  ** 0xFFA14000 - 0xFFAF0000    
  ** 0xFFA10000 - 0xFFA13FFF  Instr SR/Ca  
  ** 0xFFA08000 - 0xFFA0FFFF    
  ** 0xFFA04000 - 0xFFA07FFF    
  ** 0xFFA00000 - 0xFFA03FFF  Instr SR  
  ** 0xFF908000 - 0xFF9FFFFF    
  ** 0xFF904000 - 0xFF907FFF  Bank B SR/Ca  
  ** 0xFF900000 - 0xFF903FFF  Bank B SR  
  ** 0xFF808000 - 0xFF8FFFFF    
  ** 0xFF804000 - 0xFF807FFF  Bank A SR/Ca  
  ** 0xFF800000 - 0xFF803FFF  Bank A SR  
  ** 0xFF701000 - 0xFF7FFFFF    
  ** 0xFF700000 - 0xFF700FFF  Scratchpad
  ** 0xFF614000 - 0xFF6FFFFF    
  ** 0xFF610000 - 0xFF613FFF  Instr SR/Ca
  ** 0xFF608000 - 0xFF60FFFF    
  ** 0xFF604000 - 0xFF607FFF    
  ** 0xFF600000 - 0xFF603FFF  Instr SR
  ** 0xFF508000 - 0xFF5FFFFF    
  ** 0xFF504000 - 0xFF507FFF  Bank B SR/Ca
  ** 0xFF500000 - 0xFF503FFF  Bank B SR 
  ** 0xFF408000 - 0xFF4FFFFF    
  ** 0xFF404000 - 0xFF407FFF  Bank A SR/Ca
  ** 0xFF400000 - 0xFF403FFF  Bank A SR 
  ** 0xFEB20000 - 0xFF3FFFFF    
  ** 0xFEB00000 - 0xFEB1FFFF  L2 Shared
  ** 0xEF004000 - 0xFEAFFFFF    
  ** 0xEF002000 - 0xEF003FFF    
  ** 0xEF001000 - 0xEF001FFF    
  ** 0xEF000800 - 0xEF000FFF    
  ** 0xEF000000 - 0xEF0007FF  Boot ROM
  ** 0x30000000 - 0xEEFFFFFF    
  ** 0x2C000000 - 0x2FFFFFFF  Async 3
  ** 0x28000000 - 0x2BFFFFFF  Async 2
  ** 0x24000000 - 0x27FFFFFF  Async 1
  ** 0x20000000 - 0x23FFFFFF  Async 0
  ** 0x00000000 - 0x1FFFFFFF  SDRAM MEMORY (512MB)
  */
  
   MEM_L2_SRAM             { TYPE(RAM) START(0xFEB00000) END(0xFEB1FFFF) WIDTH(8) }
   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x2C000000) END(0x2FFFFFFF) WIDTH(8) }
   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x28000000) END(0x2BFFFFFF) WIDTH(8) }
   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x24000000) END(0x27FFFFFF) WIDTH(8) }
   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x23FFFFFF) WIDTH(8) }
   
   /*$VDSG<insert-new-memory-segments>                          */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-new-memory-segments>                          */
   
} /* MEMORY */

COMMON_MEMORY
{
   OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY/L2_and_L3_common_memory.sm)
   MASTERS(p0, p1)
   
   /*$VDSG<insert-user-ldf-commands-in-COMMON-MEMORY>           */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-user-ldf-commands-in-COMMON-MEMORY>           */
   
   SECTIONS
   {
      
      /*$VDSG<insert-new-sections-at-the-start-for-COMMON-MEMORY>  */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-start-for-COMMON-MEMORY>  */
      
      L2_sram
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML2_CM(l2_sram))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{prefersMem("internal")}(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{prefersMem("internal")}(data1))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{!prefersMem("external")}(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{!prefersMem("external")}(data1))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(constdata))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(voldata))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(noncache_code))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(data1))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l2_sram-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l2_sram-CM>  */
         
      } > MEM_L2_SRAM

      L2_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML2_CM(L2_bsz))