vdk-bf561.ldf

analog device vdsp LAN driver and examples

      ldf_heap_length = ldf_heap_end - ldf_heap_space;
#endif
   } > mem_a_l2_sram
#endif


        primio_atomic_lock
        {

            // Contains data shared between cores - Requires use of resolve.
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS($OBJECTS_CORE_A(l2_shared) $LIBRARIES_CORE_A(l2_shared))

            // Holds control variable used to ensure atomic file I/O
            // Must be in shared memory and NOT cached.
            INPUT_SECTIONS($OBJECTS_CORE_A(primio_atomic_lock) $LIBRARIES_CORE_A(primio_atomic_lock))
        } >mem_l2_shared
#if defined (USE_SDRAM)

#ifdef PARTITION_EZKIT_SDRAM
       sdram0_bank0
       {
#if defined(USE_SDRAM_STACK) && defined(USE_SDRAM_HEAP)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = STACKHEAP_SIZE,4)
#elif defined(USE_SDRAM_STACK)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = STACK_SIZE,4)
#elif defined(USE_SDRAM_HEAP)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = HEAP_SIZE,4)
#else
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_A(sdram0) $LIBRARIES_CORE_A(sdram0))
            INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
            INPUT_SECTIONS( $INPUT_BY_MEM_TYPE(program))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
#endif
       } >mem_sdram0_bank0

#if defined(USE_SDRAM_STACK) || defined(USE_SDRAM_HEAP)
    stack_heap_sdram
   {
          INPUT_SECTION_ALIGN(4)
          RESERVE_EXPAND(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length,0,4)
#if defined(USE_SDRAM_STACK) && defined(USE_SDRAM_HEAP)
          ldf_stack_space = stack_and_heap_in_sdram;
          ldf_stack_end = (ldf_stack_space + ((stack_and_heap_in_sdram_length * STACK_SIZE)/ STACKHEAP_SIZE) - 4 ) & 0xfffffffc;
          ldf_heap_space = ldf_stack_end + 4;
          ldf_heap_end = ldf_stack_space + stack_and_heap_in_sdram_length;
          ldf_heap_length = ldf_heap_end - ldf_heap_space;
#elif defined(USE_SDRAM_STACK)
          ldf_stack_space = stack_and_heap_in_sdram;
          ldf_stack_end = ldf_stack_space + stack_and_heap_in_sdram_length;
#elif defined(USE_SDRAM_HEAP)
          ldf_heap_space = stack_and_heap_in_sdram;
          ldf_heap_end = ldf_heap_space + stack_and_heap_in_sdram_length;
          ldf_heap_length = ldf_heap_end - ldf_heap_space;
#endif
   } >mem_sdram0_bank0
#endif /* USE_SDRAM_STACK || USE_SDRAM_HEAP */

       sdram0_bank1
        {
          // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data) $LIBRARIES_CORE_A(sdram_data))
          INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
          INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
          INPUT_SECTIONS( $OBJECTS_CORE_A(vtbl) $LIBRARIES_CORE_A(vtbl) )
          INPUT_SECTIONS( $OBJECTS_CORE_A(.rtti) $LIBRARIES_CORE_A(.rtti) )
          INPUT_SECTIONS( $OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))
          INPUT_SECTIONS( $OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))
        } >mem_sdram0_bank1

        sdram0_bank2
        {
          // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data) $LIBRARIES_CORE_A(sdram_data))
          INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
#if defined(__MEMINIT__)
          INPUT_SECTIONS( $OBJECTS_CORE_A(bsz_init) $LIBRARIES_CORE_A(bsz_init))
#endif
        } > mem_sdram0_bank2

        sdram0_bank2_bsz ZERO_INIT
        {
          // Bsz
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bsz) $LIBRARIES_CORE_A(sdram_bsz))
          INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
        } > mem_sdram0_bank2

#if defined(__MEMINIT__)
        .meminit { ALIGN(4) } >mem_sdram0_bank2
#endif
        sdram0_bank3
        {
          // Program Section
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
          INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
        } >mem_sdram0_bank3
#else
        sdram0
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_A(sdram0) $LIBRARIES_CORE_A(sdram0))
            INPUT_SECTIONS( $OBJECTS_CORE_A(sdram0_data) $LIBRARIES_CORE_A(sdram0_data))
#if defined(__MEMINIT__)
            INPUT_SECTIONS( $OBJS(bsz_init) $LIBS(bsz_init))
#endif
#if defined(USE_SDRAM_STACK) && defined(USE_SDRAM_HEAP)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = STACKHEAP_SIZE,4)
#elif defined(USE_SDRAM_STACK)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = STACK_SIZE,4)
#elif defined(USE_SDRAM_HEAP)
            RESERVE(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length = HEAP_SIZE,4)
#endif
            INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
            INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
            INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
            INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))
        } >mem_sdram0

        bsz_sdram0 ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_A(sdram_bsz) $LIBRARIES_CORE_A(sdram_bsz))
            INPUT_SECTIONS( $OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
        } >mem_sdram0
#if defined(__MEMINIT__)
           .meminit { ALIGN(4) } >mem_sdram0
#endif


#if defined(USE_SDRAM_STACK) || defined(USE_SDRAM_HEAP)

#  if !DATAA_CACHE && !DATAB_CACHE
#    warning Putting stack/heap into external sdram without data cache enabled can have a serious performance impact
#endif

   stack_heap_sdram
   {
           INPUT_SECTION_ALIGN(4)
#if !defined(__MEMINIT__)
           RESERVE_EXPAND(stack_and_heap_in_sdram, stack_and_heap_in_sdram_length,0,4)
#endif
#if defined(USE_SDRAM_STACK) && defined(USE_SDRAM_HEAP)
           ldf_stack_space = stack_and_heap_in_sdram;
           ldf_stack_end = (ldf_stack_space + ((stack_and_heap_in_sdram_length * STACK_SIZE)/ STACKHEAP_SIZE) - 4 ) & 0xfffffffc;
           ldf_heap_space = ldf_stack_end + 4;
           ldf_heap_end = ldf_stack_space + stack_and_heap_in_sdram_length;
           ldf_heap_length = ldf_heap_end - ldf_heap_space;
#elif defined(USE_SDRAM_STACK)
           ldf_stack_space = stack_and_heap_in_sdram;
           ldf_stack_end = ldf_stack_space + stack_and_heap_in_sdram_length;
#elif defined(USE_SDRAM_HEAP)
           ldf_heap_space = stack_and_heap_in_sdram;
           ldf_heap_end = ldf_heap_space + stack_and_heap_in_sdram_length;
           ldf_heap_length = ldf_heap_end - ldf_heap_space;
#endif
   } >mem_sdram0
#endif /* USE_SDRAM_STACK || USE_SDRAM_HEAP */

#endif /* PARTITION_EZKIT_SDRAM */
#endif /* USE_SDRAM */
    }

}
#endif

/* Core B */
#ifdef COREB
PROCESSOR p1
{
   OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
   RESOLVE(start,0xFF600000)
   KEEP(start,_main)
   KEEP(_kMaxNumThreads__3VDK)
   KEEP(_kMaxNumActiveSemaphores__3VDK)
   KEEP(_g_Sem_ThreadBaseOffset__3VDK)
   KEEP(_kMaxNumActiveDevFlags__3VDK)
   KEEP(_kMaxNumActiveMessages__3VDK)
   KEEP(_kMaxNumActiveMemoryPools__3VDK)
   KEEP(_kNumEvents__3VDK)
   KEEP(_kNumEventBits__3VDK)

    SECTIONS
    {
#if defined(__WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES) /* { */
    /* Workaround for hardware errata 05-00-0189 -
    ** "Speculative (and fetches made at boundary of reserved memory
    ** space) for instruction or data fetches may cause false
    ** protection exceptions".
    **
    ** Done by avoiding use of 76 bytes from at the end of blocks
    ** that are adjacent to reserved memory. Workaround is enabled
    ** for appropriate silicon revisions (-si-revision switch).
    */
    RESERVE(___wabb0=0xFF700FFF - 75,___lb0=76)   /* scratchpad */
#  if !INSTR_CACHE
    RESERVE(___wabb1=0xFF613FFF - 75,___lb1=76)   /* l1 instr sram/cache */
#  endif
    RESERVE(___wabb2=0xFF603FFF - 75,___lb2=76)   /* l1 instr sram */
#  if DATAB_CACHE
    RESERVE(___wabb3=0xFF503FFF - 75,___lb3=76)   /* data B sram */
#  else
    RESERVE(___wabb4=0xFF507FFF - 75,___lb4=76)   /* data B sram/cache */
#  endif
#  if DATAA_CACHE
    RESERVE(___wabb5=0xFF403FFF - 75,___lb5=76)   /* data A sram */
#  else
    RESERVE(___wabb6=0xFF407FFF - 75,___lb6=76)   /* data A sram/cache */
#  endif
#   if 0
    /*  L2 block end memory reserved for second stage loader above */
    RESERVE(___wabb7=0xFEB1FFFF - 75,___lb7=76)   /* L2 sram */
#   endif
    RESERVE(___waba9=0x3FFFFFF - 75,___la9=76)    /* EZ-Kit sdram */
#endif /*} __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES */

#if defined(USE_SCRATCHPAD_STACK) || defined(USE_SCRATCHPAD_HEAP)
   stack_and_heap_scratchpad
   {
      INPUT_SECTION_ALIGN(4)
      RESERVE(stack_and_heap_in_scratchpad, stack_and_heap_in_scratchpad_length,4)
#if defined(USE_SCRATCHPAD_STACK) && defined(USE_SCRATCHPAD_HEAP)
      ldf_stack_space = stack_and_heap_in_scratchpad;
      ldf_stack_end = (ldf_stack_space + ((stack_and_heap_in_scratchpad_length *STACK_SIZE) / STACKHEAP_SIZE) - 4 ) & 0xfffffffc;
      ldf_heap_space = ldf_stack_end + 4;
      ldf_heap_end = ldf_stack_space + stack_and_heap_in_scratchpad_length;
      ldf_heap_length = ldf_heap_end - ldf_heap_space;
#elif defined(USE_SCRATCHPAD_STACK)
      ldf_stack_space = stack_and_heap_in_scratchpad;
      ldf_stack_end = ldf_stack_space + stack_and_heap_in_scratchpad_length;
#elif defined(USE_SCRATCHPAD_HEAP)
      ldf_heap_space = stack_and_heap_in_scratchpad;
      ldf_heap_end = ldf_heap_space + stack_and_heap_in_scratchpad_length;
      ldf_heap_length = ldf_heap_end - ldf_heap_space;
#endif
   } > mem_b_l1_scratch
#endif
        sec_program
        {
            INPUT_SECTION_ALIGN(4)
            __CORE = 1;
            INPUT_SECTIONS( $LIBRARIES_CORE_B(VDK_ISR_code) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(L1_code) $LIBRARIES_CORE_B(L1_code))
            INPUT_SECTIONS( $OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
            INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
            INPUT_SECTIONS( $OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
            INPUT_SECTIONS( $INPUT_BY_MEM_TYPE(program))
        } >mem_b_l1_code

        l1_code
        {
#if INSTR_CACHE /* { */
                ___l1_code_cache = 1;
#else
                ___l1_code_cache = 0;
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $LIBRARIES_CORE_B(VDK_ISR_code) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(L1_code) $LIBRARIES_CORE_B(L1_code))
            INPUT_SECTIONS( $OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
            INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
            INPUT_SECTIONS( $INPUT_BY_MEM_TYPE(program))
#endif /* INSTR_CACHE } */
        } >mem_b_l1_code_cache

        L1_data_a
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_B(l1_data_a) $LIBRARIES_CORE_B(l1_data_a))
            INPUT_SECTIONS( $OBJECTS_CORE_B(L1_data_a) $LIBRARIES_CORE_B(L1_data_a))
            INPUT_SECTIONS( $OBJECTS_CORE_B(l1_data) $LIBRARIES_CORE_B(l1_data))
            INPUT_SECTIONS( $OBJECTS_CORE_B(L1_data) $LIBRARIES_CORE_B(L1_data))
#if !DATAA_CACHE
            ___l1_data_cache_a = 0;
#endif
            INPUT_SECTIONS( $OBJECTS_CORE_B(vtbl) $LIBRARIES_CORE_B(vtbl) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.frt) $LIBRARIES_CORE_B(.frt) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.frtl) $LIBRARIES_CORE_B(.frtl) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(ctor) $LIBRARIES_CORE_B(ctor) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(ctorl) $LIBRARIES_CORE_B(ctorl) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.gdt) $LIBRARIES_CORE_B(.gdt) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.gdtl) $LIBRARIES_CORE_B(.gdtl) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.rtti) $LIBRARIES_CORE_B(.rtti) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht) )
            INPUT_SECTIONS( $OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
            INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
            INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
            INPUT_SECTIONS( $INPUT_BY_MEM_TYPE(data1))
        } >mem_b_l1_data_a

         bsz_L1_data_a ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_B(L1_bsz) $LIBRARIES_CORE_B(L1_bsz))
            INPUT_SECTIONS( $OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
        } >mem_b_l1_data_a

	L1_data_b
        {
            INPUT_SECTION_ALIGN(4)