vdk-bf561.ldf

analog device vdsp LAN driver and examples

/*
** Default LDF for a VDK project on the ADSP-BF561.
** 
** There are configuration options that can be specified either by compiler
** flags, or by linker flags directly. These options are:
**
** __WORKAROUNDS_ENABLED
**      Defined by compiler when -workaround is used to direct LDF to
**      link with libraries that have been built with work-arounds enabled.
** USE_CACHE
**      Makes use of some L1 memory as cache. Implies the presence of at
**      least some external memory.
** USER_CRT
**    Specifies a custom or System Builder generated CRT object to use.
** COREA
**      Build a DXE for Core A (default)
** COREB
**      Build a DXE for Core B
** _ADI_LIBIO
**   Use the ADI io library (default and fast)
** _DINKUM_IO
**   Use dinkum io library (slower but more compatible). Enabled
**   by the flag -cstd-io
*/

// Setup the architecture
ARCHITECTURE(ADSP-BF561)

// Setup the search directories
SEARCH_DIR( $ADI_DSP/BLACKFIN/lib )

# if defined(USE_INSTRUCTION_CACHE) || \
     defined(USE_DATA_A_CACHE) || defined(USE_DATA_B_CACHE)
#  define USE_CACHE_PARTS 1
# else
#  define USE_CACHE_PARTS 0
#endif

#define INSTR_CACHE \
    ( defined(USE_CACHE) && \
     ( ( defined(USE_INSTRUCTION_CACHE) || !USE_CACHE_PARTS ) ) )

#define DATAA_CACHE \
    ( defined(USE_CACHE) && \
     ( ( defined(USE_DATA_A_CACHE) || defined(USE_DATA_B_CACHE) || \
         !USE_CACHE_PARTS ) ) )

#define DATAB_CACHE \
    ( defined(USE_CACHE) && \
     ( ( defined(USE_DATA_B_CACHE) || !USE_CACHE_PARTS ) ) )

# if defined(USE_INSTRUCTION_CACHE) || \
     defined(USE_DATA_A_CACHE) || defined(USE_DATA_B_CACHE)
#  define USE_CACHE_PARTS 1
# else
#  define USE_CACHE_PARTS 0
#endif

#if !defined(COREA) && !defined(COREB)
#define COREA
#endif

/* definitions related to the placement of heap and stack */
/*
** decide if to include mappings to SDRAM or not
*/
#if !defined(USE_SDRAM) && \
    ( defined(USE_CACHE) || defined(USE_SDRAM_STACK) || \
      defined(USE_SDRAM_HEAP) )
#  define USE_SDRAM
#endif


// our default stack size is small so it can fit in scratchpad leaving space
// for other things in other memory areas
#if !defined (USE_SDRAM_STACK) && !defined (USE_L1_DATA_STACK) && !defined (USE_L2_STACK) 
#define USE_SCRATCHPAD_STACK
#endif

#ifndef USE_L1_DATA_STACK
#define USE_L1_DATA_STACK (!defined(USE_SCRATCHPAD_STACK) && !defined(USE_SDRAM_STACK) && !defined (USE_L2_STACK))
#endif

#ifndef USE_L1_DATA_HEAP
#define USE_L1_DATA_HEAP  (!defined(USE_SCRATCHPAD_HEAP) && !defined(USE_SDRAM_HEAP)&& !defined (USE_L2_HEAP) )
#endif

// minimum sizes of the stack and heap allocated
#define STACK_SIZE 1K
#define HEAP_SIZE 11K
#define STACKHEAP_SIZE 12K


// Include the VDK preprocessor macros
#define VDK_LDF_
#include "VDK.h"

// Setup the VDK library preprocessor macros
#if VDK_INSTRUMENTATION_LEVEL_==2
#define VDK_IFLAG_ i
#elif VDK_INSTRUMENTATION_LEVEL_==1
#define VDK_IFLAG_ e
#else
#define VDK_IFLAG_ n
#endif

  #define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -BF561.dlb
  #define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
#ifdef __WORKAROUNDS_ENABLED
    #define RT_LIB_NAME(x) lib ## x ## y.dlb
    #define RT_LIB_NAME_MT(x) lib ## x ## mty.dlb
    #define RT_OBJ_NAME(x) x ## y.doj
    #define RT_OBJ_NAME_MT(x) x ## mty.doj
  #ifdef __ADI_LIBEH__
    #define RT_LIB_NAME_EH(x) lib ## x ## yx.dlb
    #define RT_LIB_NAME_EH_MT(x) lib ## x ## mtyx.dlb
  #else /* __ADI_LIBEH__ */
    #define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
    #define RT_LIB_NAME_EH_MT(x) lib ## x ## mty.dlb
  #endif
#else /* __WORKAROUNDS_ENABLED */
    #define RT_LIB_NAME(x) lib ## x ## .dlb
    #define RT_LIB_NAME_MT(x) lib ## x ## mt.dlb
    #define RT_OBJ_NAME(x) x ## .doj
    #define RT_OBJ_NAME_MT(x) x ## mt.doj
  #ifdef __ADI_LIBEH__
    #define RT_LIB_NAME_EH(x) lib ## x ## x.dlb
    #define RT_LIB_NAME_EH_MT(x) lib ## x ## mtx.dlb
  #else /* __ADI_LIBEH__ */
    #define RT_LIB_NAME_EH(x) lib ## x ## .dlb
    #define RT_LIB_NAME_EH_MT(x) lib ## x ## mt.dlb
  #endif
#endif /* __WORKAROUNDS_ENABLED */

#ifdef USER_CRT
  #define CRT USER_CRT
#else
  #define CRT RT_OBJ_NAME_MT(crtsfc561)
#endif

#if defined(USER_CPLBTAB)
   #define CPLBTAB USER_CPLBTAB
#else
   #ifdef COREA
      #define CPLBTAB cplbtab561a.doj
   #else
      #define CPLBTAB cplbtab561b.doj
   #endif
#endif

#define MEMINIT __initsbsz561.doj

$LIBRARIES =
   RT_LIB_NAME_MT(small561)
   ,MEMINIT
#if defined(_DINKUM_IO)
   ,RT_LIB_NAME_MT(c561)         /* ANSI C (and IO) run-time library */
   ,RT_LIB_NAME_MT(io561)        /* Fast IO and host IO support      */
#else
   ,RT_LIB_NAME_MT(io561)        /* Fast IO and host IO support      */
   ,RT_LIB_NAME_MT(c561)         /* ANSI C (and IO) run-time library */
#endif
#if defined(USE_FILEIO)
   ,RT_LIB_NAME_MT(rt_fileio561)    /* Run-time Support with File IO    */
#else
   ,RT_LIB_NAME_MT(rt561)           /* Run-time Support without File IO */
#endif
   ,RT_LIB_NAME_MT(event561)
   ,RT_LIB_NAME_EH_MT(cpp561)
   ,RT_LIB_NAME_EH_MT(cpprt561)
   ,RT_LIB_NAME_MT(x561)
#if defined(IEEEFP)
   ,RT_LIB_NAME(sftflt561)    /* IEEE floating-point emulation    */
#endif
   ,RT_LIB_NAME(f64ieee561)   /* 64-bit floating-point support    */
   ,RT_LIB_NAME(dsp561)       /* DSP run-time library             */
#if !defined(IEEEFP)
   ,RT_LIB_NAME(sftflt561)    /* IEEE floating-point emulation    */
#endif
   ,RT_LIB_NAME(etsi561)
   ,RT_LIB_NAME(ssl561_vdk)
   ,RT_LIB_NAME(drv561)
   ,RT_OBJ_NAME_MT(idle561)
   ,RT_LIB_NAME_MT(rt_fileio561)
   ;

$BASE_LIBRARIES = $LIBRARIES;

$LIBS = TMK-BF561.dlb, VDK_LIB_NAME_(CORE), VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;

$OBJS = CRT, $COMMAND_LINE_OBJECTS, CPLBTAB, RT_OBJ_NAME_MT(crtn561);

#ifdef COREA
$OBJECTS_CORE_A = $OBJS;
$LIBRARIES_CORE_A = $LIBS ;
#else
$OBJECTS_CORE_B = $OBJS;
$LIBRARIES_CORE_B = $LIBS ;
#endif

$OBJS_LIBS_INTERNAL= 
        $OBJS{prefersMem("internal")},
	$LIBS{prefersMem("internal")};
$OBJS_LIBS_NOT_EXTERNAL= 
	$OBJS{!prefersMem("external")},
	$LIBS{!prefersMem("external")};
$INPUT_BY_MEM_TYPE =
	$OBJS_LIBS_INTERNAL,
	$OBJS_LIBS_NOT_EXTERNAL,
	$OBJS, 
	$LIBS;
/*
** Memory map.
**
** The known memory spaces are as follows:
**
** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers (2MB per core)
** 0xFFC00000 - 0xFFDFFFFF  System MMR registers (2MB)
** CoreA:
** 0xFFB01000 - 0xFFBFFFFF  Reserved
** 0xFFB00000 - 0xFFB00FFF  Scratch SRAM (4K)
** 0xFFA14000 - 0xFFAFFFFF  Reserved
** 0xFFA10000 - 0xFFA13FFF  Code SRAM / cache (16K)
** 0xFFA04000 - 0xFFA0FFFF  Reserved
** 0xFFA00000 - 0xFFA03FFF  Code SRAM (16K)
** 0xFF908000 - 0xFF9FFFFF  Reserved
** 0xFF904000 - 0xFF907FFF  Data Bank B SRAM / cache (16K)
** 0xFF900000 - 0xFF903FFF  Data Bank B SRAM (16K)
** 0xFF804000 - 0xFF807FFF  Data Bank A SRAM / cache (16K)
** 0xFF800000 - 0xFF803FFF  Data Bank A SRAM (16K)
** 0xFF400000 - 0xFF7FFFFF  Reserved
** CoreB:
** 0xFF701000 - 0xFFBFFFFF  Reserved
** 0xFF700000 - 0xFF700FFF  Scratch SRAM (4K)
** 0xFF614000 - 0xFF6FFFFF  Reserved
** 0xFF610000 - 0xFF613FFF  Code SRAM / cache (16K)
** 0xFF604000 - 0xFF60FFFF  Reserved
** 0xFF600000 - 0xFF603FFF  Code SRAM (16K)
** 0xFF508000 - 0xFF5FFFFF  Reserved
** 0xFF504000 - 0xFF507FFF  Data Bank B SRAM / cache (16K)
** 0xFF500000 - 0xFF503FFF  Data Bank B SRAM (16K)
** 0xFF404000 - 0xFF407FFF  Data Bank A SRAM / cache (16K)
** 0xFF400000 - 0xFF403FFF  Data Bank A SRAM (16K)
** Shared mem:
** 0xFFB20000 - 0xFF3FFFFF  Reserved
** 0xFFB00000 - 0xFFB1FFFF  L2 SRAM (128K)
** 0xEF000800 - 0xFEAFFFFF  Reserved
** 0xEF000000 - 0xEF007FFF  Boot ROM
** 0x30000000 - 0xEEFFFFFF  Reserved
** 0x2C000000 - 0x2FFFFFFF  ASYNC MEMORY BANK 3 (64MB)
** 0x20200000 - 0x202FFFFF  ASYNC MEMORY BANK 2 (1MB)
** 0x20100000 - 0x201FFFFF  ASYNC MEMORY BANK 1 (1MB)
** 0x20000000 - 0x200FFFFF  ASYNC MEMORY BANK 0 (1MB)
** 0x00000000 - 0x04000000  EZKIT SDRAM MEMORY (64MB)
** 0x00000000 - 0x1FFFFFFF  SDRAM MEMORY (0-512MB)
**
** Notes:
** FEB1FC00->FEB1FFFF : Reseved in boot Phase for 2nd stage boot loader
**
*/

MEMORY
{
/* L1 memory Core A */
mem_a_l1_scratch      { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
mem_a_l1_code         { TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) }
mem_a_l1_code_cache   { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }

#if DATAB_CACHE
mem_a_l1_data_b       { TYPE(RAM) START(0xFF900000) END(0xFF903FFF) WIDTH(8) }
mem_a_l1_data_b_cache { TYPE(RAM) START(0xFF904000) END(0xFF907FFF) WIDTH(8) }
#else
mem_a_l1_data_b       { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
#endif
#if DATAA_CACHE
mem_a_l1_data_a_cache { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }
mem_a_l1_data_a       { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }
#else
mem_a_l1_data_a       { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
#endif


/* L1 memory Core B */
mem_b_l1_scratch      { TYPE(RAM) START(0xFF700000) END(0xFF700FFF) WIDTH(8) }
mem_b_l1_code         { TYPE(RAM) START(0xFF600000) END(0xFF603FFF) WIDTH(8) }
mem_b_l1_code_cache   { TYPE(RAM) START(0xFF610000) END(0xFF613FFF) WIDTH(8) }

#if DATAB_CACHE
mem_b_l1_data_b       { TYPE(RAM) START(0xFF500000) END(0xFF503FFF) WIDTH(8) }
mem_b_l1_data_b_cache { TYPE(RAM) START(0xFF504000) END(0xFF507FFF) WIDTH(8) }
#else
mem_b_l1_data_b       { TYPE(RAM) START(0xFF500000) END(0xFF507FFF) WIDTH(8) }
#endif
#if DATAA_CACHE
mem_b_l1_data_a       { TYPE(RAM) START(0xFF400000) END(0xFF403FFF) WIDTH(8) }
mem_b_l1_data_a_cache { TYPE(RAM) START(0xFF404000) END(0xFF407FFF) WIDTH(8) }
#else
mem_b_l1_data_a       { TYPE(RAM) START(0xFF400000) END(0xFF407FFF) WIDTH(8) }
#endif

/* L2 SRAM - 128K. */
/* For convenience, we divide this space into: */
/* Core B only - 32K */
/* Core A only - 32K */
/* Shared = 64K */
/* And then subdivide each core-only area for program layout. */

/* L2 memory Core B - FEB00000 to FEB07FFF */