📄 spokepov.lss
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340: 80 91 88 00 lds r24, 0x0088
344: 84 30 cpi r24, 0x04 ; 4
346: 08 f4 brcc .+2 ; 0x34a <__vector_2+0x4c>
348: d1 c0 rjmp .+418 ; 0x4ec <__vector_2+0x1ee>
34a: 80 91 88 00 lds r24, 0x0088
34e: 8b bd out 0x2b, r24 ; 43
350: 82 b7 in r24, 0x32 ; 50
352: 8a bd out 0x2a, r24 ; 42
354: 12 be out 0x32, r1 ; 50
356: 80 91 67 00 lds r24, 0x0067
35a: 8f 5f subi r24, 0xFF ; 255
35c: 80 93 67 00 sts 0x0067, r24
360: 20 e0 ldi r18, 0x00 ; 0
362: 80 91 67 00 lds r24, 0x0067
366: 8a 33 cpi r24, 0x3A ; 58
368: b8 f0 brcs .+46 ; 0x398 <__vector_2+0x9a>
36a: 90 e3 ldi r25, 0x30 ; 48
36c: e2 2f mov r30, r18
36e: ff 27 eor r31, r31
370: e9 59 subi r30, 0x99 ; 153
372: ff 4f sbci r31, 0xFF ; 255
374: 90 83 st Z, r25
376: 23 30 cpi r18, 0x03 ; 3
378: 41 f0 breq .+16 ; 0x38a <__vector_2+0x8c>
37a: 2f 5f subi r18, 0xFF ; 255
37c: e2 2f mov r30, r18
37e: ff 27 eor r31, r31
380: e9 59 subi r30, 0x99 ; 153
382: ff 4f sbci r31, 0xFF ; 255
384: 80 81 ld r24, Z
386: 8f 5f subi r24, 0xFF ; 255
388: 80 83 st Z, r24
38a: e2 2f mov r30, r18
38c: ff 27 eor r31, r31
38e: e9 59 subi r30, 0x99 ; 153
390: ff 4f sbci r31, 0xFF ; 255
392: 80 81 ld r24, Z
394: 8a 33 cpi r24, 0x3A ; 58
396: 50 f7 brcc .-44 ; 0x36c <__vector_2+0x6e>
398: 80 91 62 00 lds r24, 0x0062
39c: 80 31 cpi r24, 0x10 ; 16
39e: 08 f4 brcc .+2 ; 0x3a2 <__vector_2+0xa4>
3a0: 98 c0 rjmp .+304 ; 0x4d2 <__vector_2+0x1d4>
3a2: 80 91 62 00 lds r24, 0x0062
3a6: 80 51 subi r24, 0x10 ; 16
3a8: 80 93 62 00 sts 0x0062, r24
3ac: 80 91 60 00 lds r24, 0x0060
3b0: 8f 5f subi r24, 0xFF ; 255
3b2: 8f 70 andi r24, 0x0F ; 15
3b4: 80 93 60 00 sts 0x0060, r24
3b8: c0 91 60 00 lds r28, 0x0060
3bc: cc 23 and r28, r28
3be: 09 f0 breq .+2 ; 0x3c2 <__vector_2+0xc4>
3c0: 88 c0 rjmp .+272 ; 0x4d2 <__vector_2+0x1d4>
3c2: 80 91 61 00 lds r24, 0x0061
3c6: 8f 5f subi r24, 0xFF ; 255
3c8: 80 93 61 00 sts 0x0061, r24
3cc: 80 91 61 00 lds r24, 0x0061
3d0: 86 30 cpi r24, 0x06 ; 6
3d2: 11 f4 brne .+4 ; 0x3d8 <__vector_2+0xda>
3d4: c0 93 61 00 sts 0x0061, r28
3d8: 80 91 61 00 lds r24, 0x0061
3dc: e8 2f mov r30, r24
3de: ff 27 eor r31, r31
3e0: e5 57 subi r30, 0x75 ; 117
3e2: ff 4f sbci r31, 0xFF ; 255
3e4: c8 95 lpm
3e6: 20 2d mov r18, r0
3e8: 82 2f mov r24, r18
3ea: 99 27 eor r25, r25
3ec: 86 5b subi r24, 0xB6 ; 182
3ee: 9f 4f sbci r25, 0xFF ; 255
3f0: 40 e1 ldi r20, 0x10 ; 16
3f2: 50 e0 ldi r21, 0x00 ; 0
3f4: 68 2f mov r22, r24
3f6: 79 2f mov r23, r25
3f8: 80 e9 ldi r24, 0x90 ; 144
3fa: 90 e0 ldi r25, 0x00 ; 0
3fc: 9a d1 rcall .+820 ; 0x732 <memcpy_P>
3fe: c0 93 74 00 sts 0x0074, r28
402: 80 91 61 00 lds r24, 0x0061
406: e8 2f mov r30, r24
408: ff 27 eor r31, r31
40a: ee 5b subi r30, 0xBE ; 190
40c: ff 4f sbci r31, 0xFF ; 255
40e: c8 95 lpm
410: 20 2d mov r18, r0
412: 22 23 and r18, r18
414: 61 f0 breq .+24 ; 0x42e <__vector_2+0x130>
416: 82 2f mov r24, r18
418: 99 27 eor r25, r25
41a: 8f 70 andi r24, 0x0F ; 15
41c: 90 70 andi r25, 0x00 ; 0
41e: 80 57 subi r24, 0x70 ; 112
420: 9f 4f sbci r25, 0xFF ; 255
422: 90 93 76 00 sts 0x0076, r25
426: 80 93 75 00 sts 0x0075, r24
42a: 20 93 74 00 sts 0x0074, r18
42e: c0 91 61 00 lds r28, 0x0061
432: cf 5f subi r28, 0xFF ; 255
434: 0c 2f mov r16, r28
436: 11 27 eor r17, r17
438: f1 2f mov r31, r17
43a: e0 2f mov r30, r16
43c: e5 57 subi r30, 0x75 ; 117
43e: ff 4f sbci r31, 0xFF ; 255
440: c8 95 lpm
442: 20 2d mov r18, r0
444: 82 2f mov r24, r18
446: 99 27 eor r25, r25
448: 86 5b subi r24, 0xB6 ; 182
44a: 9f 4f sbci r25, 0xFF ; 255
44c: 40 e1 ldi r20, 0x10 ; 16
44e: 50 e0 ldi r21, 0x00 ; 0
450: 68 2f mov r22, r24
452: 79 2f mov r23, r25
454: 80 ea ldi r24, 0xA0 ; 160
456: 90 e0 ldi r25, 0x00 ; 0
458: 6c d1 rcall .+728 ; 0x732 <memcpy_P>
45a: 0e 5b subi r16, 0xBE ; 190
45c: 1f 4f sbci r17, 0xFF ; 255
45e: f1 2f mov r31, r17
460: e0 2f mov r30, r16
462: c8 95 lpm
464: 20 2d mov r18, r0
466: 22 23 and r18, r18
468: 61 f0 breq .+24 ; 0x482 <__vector_2+0x184>
46a: 82 2f mov r24, r18
46c: 99 27 eor r25, r25
46e: 8f 70 andi r24, 0x0F ; 15
470: 90 70 andi r25, 0x00 ; 0
472: 80 56 subi r24, 0x60 ; 96
474: 9f 4f sbci r25, 0xFF ; 255
476: 90 93 76 00 sts 0x0076, r25
47a: 80 93 75 00 sts 0x0075, r24
47e: 20 93 74 00 sts 0x0074, r18
482: cf 5f subi r28, 0xFF ; 255
484: 0c 2f mov r16, r28
486: 11 27 eor r17, r17
488: f1 2f mov r31, r17
48a: e0 2f mov r30, r16
48c: e5 57 subi r30, 0x75 ; 117
48e: ff 4f sbci r31, 0xFF ; 255
490: c8 95 lpm
492: 20 2d mov r18, r0
494: 82 2f mov r24, r18
496: 99 27 eor r25, r25
498: 86 5b subi r24, 0xB6 ; 182
49a: 9f 4f sbci r25, 0xFF ; 255
49c: 40 e1 ldi r20, 0x10 ; 16
49e: 50 e0 ldi r21, 0x00 ; 0
4a0: 68 2f mov r22, r24
4a2: 79 2f mov r23, r25
4a4: 87 e7 ldi r24, 0x77 ; 119
4a6: 90 e0 ldi r25, 0x00 ; 0
4a8: 44 d1 rcall .+648 ; 0x732 <memcpy_P>
4aa: 0e 5b subi r16, 0xBE ; 190
4ac: 1f 4f sbci r17, 0xFF ; 255
4ae: f1 2f mov r31, r17
4b0: e0 2f mov r30, r16
4b2: c8 95 lpm
4b4: 00 2d mov r16, r0
4b6: 00 23 and r16, r16
4b8: 61 f0 breq .+24 ; 0x4d2 <__vector_2+0x1d4>
4ba: 80 2f mov r24, r16
4bc: 99 27 eor r25, r25
4be: 8f 70 andi r24, 0x0F ; 15
4c0: 90 70 andi r25, 0x00 ; 0
4c2: 89 58 subi r24, 0x89 ; 137
4c4: 9f 4f sbci r25, 0xFF ; 255
4c6: 90 93 76 00 sts 0x0076, r25
4ca: 80 93 75 00 sts 0x0075, r24
4ce: 00 93 74 00 sts 0x0074, r16
4d2: 8f e1 ldi r24, 0x1F ; 31
4d4: 80 93 6f 00 sts 0x006F, r24
4d8: 8f e0 ldi r24, 0x0F ; 15
4da: 80 93 6e 00 sts 0x006E, r24
4de: 8e b5 in r24, 0x2e ; 46
4e0: 81 60 ori r24, 0x01 ; 1
4e2: 8e bd out 0x2e, r24 ; 46
4e4: 89 b7 in r24, 0x39 ; 57
4e6: 80 64 ori r24, 0x40 ; 64
4e8: 89 bf out 0x39, r24 ; 57
4ea: 0e c0 rjmp .+28 ; 0x508 <__vector_2+0x20a>
4ec: 8c ef ldi r24, 0xFC ; 252
4ee: 38 de rcall .-912 ; 0x160 <set_all>
4f0: 8e b5 in r24, 0x2e ; 46
4f2: 8e 7f andi r24, 0xFE ; 254
4f4: 8e bd out 0x2e, r24 ; 46
4f6: 80 e1 ldi r24, 0x10 ; 16
4f8: 80 93 62 00 sts 0x0062, r24
4fc: 8f e0 ldi r24, 0x0F ; 15
4fe: 80 93 60 00 sts 0x0060, r24
502: 8f ef ldi r24, 0xFF ; 255
504: 80 93 61 00 sts 0x0061, r24
508: 10 92 89 00 sts 0x0089, r1
50c: 10 92 88 00 sts 0x0088, r1
510: 10 92 87 00 sts 0x0087, r1
514: ff 91 pop r31
516: ef 91 pop r30
518: cf 91 pop r28
51a: bf 91 pop r27
51c: af 91 pop r26
51e: 9f 91 pop r25
520: 8f 91 pop r24
522: 7f 91 pop r23
524: 6f 91 pop r22
526: 5f 91 pop r21
528: 4f 91 pop r20
52a: 3f 91 pop r19
52c: 2f 91 pop r18
52e: 1f 91 pop r17
530: 0f 91 pop r16
532: 0f 90 pop r0
534: 0f be out 0x3f, r0 ; 63
536: 0f 90 pop r0
538: 1f 90 pop r1
53a: 18 95 reti
0000053c <ioinit>:
53c: 83 e7 ldi r24, 0x73 ; 115
53e: 81 bb out 0x11, r24 ; 17
540: 8f ed ldi r24, 0xDF ; 223
542: 87 bb out 0x17, r24 ; 23
544: 80 e1 ldi r24, 0x10 ; 16
546: 88 bb out 0x18, r24 ; 24
548: 8c e4 ldi r24, 0x4C ; 76
54a: 82 bb out 0x12, r24 ; 18
54c: 98 e0 ldi r25, 0x08 ; 8
54e: 95 bf out 0x35, r25 ; 53
550: 80 ec ldi r24, 0xC0 ; 192
552: 8b bf out 0x3b, r24 ; 59
554: 10 be out 0x30, r1 ; 48
556: 84 e0 ldi r24, 0x04 ; 4
558: 83 bf out 0x33, r24 ; 51
55a: 89 b7 in r24, 0x39 ; 57
55c: 82 60 ori r24, 0x02 ; 2
55e: 89 bf out 0x39, r24 ; 57
560: 1f bc out 0x2f, r1 ; 47
562: 9e bd out 0x2e, r25 ; 46
564: 10 92 87 00 sts 0x0087, r1
568: 10 92 89 00 sts 0x0089, r1
56c: 10 92 88 00 sts 0x0088, r1
570: 08 95 ret
00000572 <main>:
}
int main(void) {
572: cf ed ldi r28, 0xDF ; 223
574: d0 e0 ldi r29, 0x00 ; 0
576: de bf out 0x3e, r29 ; 62
578: cd bf out 0x3d, r28 ; 61
uint8_t cmd; // the reason we reset
// MCUSR is the MCU Status Register (page 40). It tells us
// why we reset, and a reset is the only way to get here.
cmd = MCUSR;
57a: 84 b7 in r24, 0x34 ; 52
// The first order of business is to tell the chip that
// we've got things under control.
MCUSR = 0;
57c: 14 be out 0x34, r1 ; 52
// Turn on watchdog timer immediately, this protects against
// a 'stuck' system by resetting it.
// WDTCSR is the Watchdog Timer Control Register (page 45).
// We set it so that it'll generate a watchdog interrupt
// every second. The idea is that if things mess up,
// the watchdog will kickstart us.
WDTCSR = _BV(WDE) | _BV(WDP2) | _BV(WDP1); // 1 second
57e: 8e e0 ldi r24, 0x0E ; 14
580: 81 bd out 0x21, r24 ; 33
// Initialize the various pins of the ATMEL, and set up
// the interrupts.
ioinit();
582: dc df rcall .-72 ; 0x53c <ioinit>
// Show that we are active.
set_all(~0x01);
584: 8e ef ldi r24, 0xFE ; 254
586: ec dd rcall .-1064 ; 0x160 <set_all>
// enable the interrupts. I think this is not needed
// since it'll immediately be done by the loop, below.
sei();
588: 78 94 sei
// Loop until we timeout, at which point the ATMEL is
// put to sleep. If the communications routine timed
// out, or the user pressed the button for >500ms,
// then sensor_timer will be 0xFFFF and we'll immediately
// sleep.
// Change to for (;;) to see if it makes any difference
for (;;) {
// Reset the watchdog Timer.
//
// QUESTION: What's with toggling the PD0 output line here?
// it doesn't seem to be connected to anything according to
// the circuit diagram...
// *** PORTD |= 0x1;
asm("wdr");
58a: a8 95 wdr
// *** PORTD &= ~0x1;
// If the sensor_timer (incremented by TIMER0) maxes out
// (in about 3 minutes), then sleep everything.
if (sensor_timer.bytes.high_byte == 0xFF) {
58c: 80 91 89 00 lds r24, 0x0089
590: 8f 3f cpi r24, 0xFF ; 255
592: 71 f4 brne .+28 ; 0x5b0 <main+0x3e>
// Avoid pesky interruptions
cli();
594: f8 94 cli
// Turn off all LEDs - I guess LED 0 is one of the "invisible ones"
set_all(0xFF);
596: e4 dd rcall .-1080 ; 0x160 <set_all>
// Turn off power to the Hall Effect sensor.
SENSOR_PORT &= ~_BV(SENSORPOWER);
598: 96 98 cbi 0x12, 6 ; 18
// Deselect EEPROM
SPIEE_CS_PORT |= _BV(SPIEE_CS); // pull CS high to deselect
59a: c4 9a sbi 0x18, 4 ; 24
// Turn off Watchdog (must be restarted when we get the wakeup)
// Wakeup will be via the button interrupt.
WDTCSR |= _BV(WDCE) | _BV(WDE);
59c: 81 b5 in r24, 0x21 ; 33
59e: 88 61 ori r24, 0x18 ; 24
5a0: 81 bd out 0x21, r24 ; 33
WDTCSR = 0;
5a2: 11 bc out 0x21, r1 ; 33
MCUCR |= _BV(SM1) | _BV(SM0) | _BV(SE);
5a4: 85 b7 in r24, 0x35 ; 53
5a6: 80 67 ori r24, 0x70 ; 112
5a8: 85 bf out 0x35, r24 ; 53
// Re-enable interrupts so we can get the wakeup!
sei();
5aa: 78 94 sei
// Go into sleep mode
asm("sleep");
5ac: 88 95 sleep
5ae: ed cf rjmp .-38 ; 0x58a <main+0x18>
} else {
// Do we have dynamic updating to do?
#ifdef DYNAMIC
uint8_t tBytes; // Number of bytes to transfer
// Use unions to overlay variables and save some space
union {
char *fPtr; // from pointer
var16bit divisor; // the divisor for RPM
} a;
union {
char *tPtr; // to pointer
char *divTable; // divisor table
} b;
// Update the dynamic data display
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