📄 conf_tny.lst
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A51 MACRO ASSEMBLER CONF_TNY 12/09/2008 16:32:51 PAGE 1
MACRO ASSEMBLER A51 V7.07
OBJECT MODULE PLACED IN Conf_tny.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE Conf_tny.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the RTX-51 TINY Real-Time Operating System Package
4 ; Copyright KEIL ELEKTRONIK GmbH and Keil Software, Inc. 1991-2002
5 ; Version 2.01
6 ;------------------------------------------------------------------------------
7 ; CONF_TNY.A51: This code allows the configuration of the
8 ; RTX-51 TINY Real-Time Operating System
9 ;
10 ; Copy this file to your project folder and add the copy to your uVision2
11 ; project. You can customize several parameters of RTX51 Tiny within this
12 ; configuration file.
13 ;
14 ; If you use command line tools, translate this file with:
15 ;
16 ; Ax51 CONF_TNY.A51
17 ;
18 ; If you use command line tools, link the modified CONF_TNY.OBJ file to
19 ; your application with:
20 ;
21 ; Lx51 <your object file list>, CONF_TNY.OBJ <controls>
22 ;
23 ;------------------------------------------------------------------------------
24 ;
25 ; RTX-51 TINY Hardware-Timer
26 ; ==========================
27 ;
28 ; With the following EQU statements the initialization of the RTX-51 TINY
29 ; Hardware-Timer can be defined (RTX-51 TINY uses the 8051 Timer 0 for
30 ; controlling RTX-51 software timers).
31 ;
32 ; Define the register bank used for the timer interrupt.
0001 33 INT_REGBANK EQU 1 ; default is Registerbank 1
34 ;
35 ; Define Hardware-Timer tick time in 8051 machine cycles.
1A0B 36 INT_CLOCK EQU 6667 ; default is 10000 cycles
37 ;INT_CLOCK = 期望值(uS)*时钟频率(Hz)/12000000
38 ;本项目 期望值(uS) = 10000 即每10mS时钟中断一次
39 ; 时钟频率(Hz) = 8MHz
40 ;
41 ; Define Round-Robin Timeout in Hardware-Timer ticks.
0000 42 TIMESHARING EQU 0 ; default is 5 Hardware-Timer ticks.
43 ; ; 0 disables Round-Robin Task Switching
44 ;
45 ; Long User Interrupt Routines: set to 1 if your application contains
46 ; user interrupt functions that may take longer than a hardware timer
47 ; interval for execution.
0000 48 LONG_USR_INTR EQU 0 ; 0 user interrupts execute fast.
49 ; ; 1 user interrupts take long execution times.
50 ;
51 ;
52 ;------------------------------------------------------------------------------
53 ;
54 ; USER CODE FOR 8051 HARDWARE TIMER INTERRUPT
55 ; ===========================================
56 ;
57 ; The following macro defines the code executed on a hardware timer interrupt.
58 ;
A51 MACRO ASSEMBLER CONF_TNY 12/09/2008 16:32:51 PAGE 2
59 ; Define instructions executed on a hardware timer interrupt.
60 HW_TIMER_CODE MACRO
61 ; Empty Macro by default
62 RETI
63 ENDM
64 ;
65 ;
66 ;------------------------------------------------------------------------------
67 ;
68 ; CODE BANKING SUPPORT
69 ; ====================
70 ;
71 ; The following EQU statement controls the code banking support for RTX51 TINY.
72 ;
73 ; Enable or disable code banking support
0000 74 CODE_BANKING EQU 0 ; 0 (default) application uses no code banking
75 ; ; 1 application uses code banking
76 ;
77 ;------------------------------------------------------------------------------
78 ;
79 ; RTX-51 TINY Stack Space
80 ; =======================
81 ;
82 ; The following EQU statements defines the size of the internal RAM used
83 ; for stack area and the minimum free space on the stack. A macro defines
84 ; the code executed when there is there is not enough free stack on the
85 ; CPU stack.
86 ;
87 ; Define the highest RAM address used for CPU stack
00FF 88 RAMTOP EQU 0FFH ; default is address (256-1)
89 ;
0014 90 FREE_STACK EQU 20 ; default is 20 bytes free space on stack
91 ; ; the value 0 disables stack checking
92 ;
93 STACK_ERROR MACRO
94 CLR EA ; disable interrupts
95 SJMP $ ; endless loop if stack space is exhausted
96 ENDM
97 ;
98 ;
99 ;------------------------------------------------------------------------------
100 ;
101 ; 8051 CPU IDLE CODE
102 ; ==================
103 ;
104 ; Many 8051 devices provide an IDLE MODE that reduces power consumption and
105 ; EMC. The following macro defines the code executed when there is no
106 ; ready task in the system. The code must set the CPU into an IDLE MODE
107 ; that stops instruction execution until an 8051 hardware interrupt occurs.
108 ;
109
110 ; Disable or Enable CPU_IDLE CODE
0000 111 CPU_IDLE_CODE EQU 0 ; 0 CPU_IDLE MACRO is not inserted
112 ; 1 CPU_IDLE MACRO is executed
113
0087 114 PCON DATA 087H ; Power Control SFR on most 8051 devices
115
116 ; Stop CPU execution until hardware interrupt; executed when there is no
117 ; active task in the system.
118 CPU_IDLE MACRO
119 ORL PCON,#1 ; set 8051 CPU to IDLE
120 ENDM
121 ;
122 ;
123 ;------------------------------------------------------------------------------
124 ;----------------- !!! End of User Configuration Part !!! ------------------
A51 MACRO ASSEMBLER CONF_TNY 12/09/2008 16:32:51 PAGE 3
125 ;----------------- !!! Do not modify code sections below !!! ------------------
126 ;------------------------------------------------------------------------------
127
128 ; SFR Symbols
00D0 129 PSW DATA 0D0H
00E0 130 ACC DATA 0E0H
00F0 131 B DATA 0F0H
0081 132 SP DATA 81H
0082 133 DPL DATA 82H
0083 134 DPH DATA 83H
0088 135 TCON DATA 88H
0089 136 TMOD DATA 89H
008A 137 TL0 DATA 8AH
008B 138 TL1 DATA 8BH
008C 139 TH0 DATA 8CH
008D 140 TH1 DATA 8DH
00A8 141 IE DATA 0A8H
142
143 ; TCON
008F 144 TF1 BIT 8FH
008E 145 TR1 BIT 8EH
008D 146 TF0 BIT 8DH
008C 147 TR0 BIT 8CH
008B 148 IE1 BIT 8BH
008A 149 IT1 BIT 8AH
0089 150 IE0 BIT 89H
0088 151 IT0 BIT 88H
152 ; IE
00AF 153 EA BIT 0AFH
00AC 154 ES BIT 0ACH
00AB 155 ET1 BIT 0ABH
00AA 156 EX1 BIT 0AAH
00A9 157 ET0 BIT 0A9H
00A8 158 EX0 BIT 0A8H
159
160 ; Check Configuration Values
161
162
163 NAME ?RTX51_TINY_KERNAL
164
165 PUBLIC ?RTX_CURRENTTASK
166 PUBLIC ?RTX_RAMTOP
167 PUBLIC os_switch_task
168 PUBLIC ?RTX?SET_ISR
169
170 EXTRN NUMBER (?RTX_MAXTASKN) ; max Task Number
171
00FF 172 ?RTX_RAMTOP EQU RAMTOP
E5F5 173 ?RTX_CLOCK EQU -INT_CLOCK
174
0008 175 ?RTX_REGISTERBANK EQU INT_REGBANK * 8
---- 176 DSEG AT ?RTX_REGISTERBANK
0008 177 DS 2 ; temporary space
000A 178 ?RTX_SAVEACC: DS 1
REG 179 saveacc EQU R2 ; for access in interrupt service routine
000B 180 ?RTX_SAVEPSW: DS 1
REG 181 savepsw EQU R3 ; for access in interrupt service routine
000C 182 ?RTX_CURRENTTASK: DS 1
REG 183 currenttask EQU R4 ; for access in interrupt service routine
184
185 IF (TIMESHARING <> 0)
?RTX_ROBINTIME: DS 1
robintime EQU R5 ; for access in interrupt service routine
ENDIF
189
190 IF (CODE_BANKING <> 0)
A51 MACRO ASSEMBLER CONF_TNY 12/09/2008 16:32:51 PAGE 4
EXTRN DATA (?B_CURRENTBANK)
EXTRN CODE (?B_RESTORE_BANK)
ENDIF
194
195
196 ;------------------------------------------------
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