i2c.h

Z228芯片是ARM926ej-s的内核

/********************************************/
/* I2CFunc.c: the I2C module API define    .*/
/* Author   : qzsu							*/
/* Time     : 2006-08-21					*/
/********************************************/

#ifndef I2C_H
#define I2C_H

#include <stdlib.h>
#include <stdio.h>

#define PIN_CFG_REG		((volatile int *)(SYSTEM_BASE+0x10C  ))

#define IIC_BASE		0x20036000
#define IIC_CON			((volatile int *)(IIC_BASE+0x00  ))
#define IIC_TAR			((volatile int *)(IIC_BASE+0x04  ))
#define IIC_SAR			((volatile int *)(IIC_BASE+0x08  ))
#define IIC_HS_MADDR		((volatile int *)(IIC_BASE+0x0c  ))
#define IIC_DATA_CMD		((volatile int *)(IIC_BASE+0x10  ))
#define IIC_SS_HCNT		((volatile int *)(IIC_BASE+0x14  ))
#define IIC_SS_LCNT		((volatile int *)(IIC_BASE+0x18  ))
#define IIC_FS_HCNT		((volatile int *)(IIC_BASE+0x1c  ))
#define IIC_FS_LCNT		((volatile int *)(IIC_BASE+0x20  ))
#define IIC_HS_HCNT		((volatile int *)(IIC_BASE+0x24  ))
#define IIC_HS_LCNT		((volatile int *)(IIC_BASE+0x28  ))
#define IIC_INTR_STAT	((volatile int *)(IIC_BASE+0x2c  ))
#define IIC_INTR_MASK	((volatile int *)(IIC_BASE+0x30  ))
#define IIC_RAW_INTR_STAT		((volatile int *)(IIC_BASE+0x34  ))
#define IIC_RX_TL		((volatile int *)(IIC_BASE+0x38  ))
#define IIC_TX_TL		((volatile int *)(IIC_BASE+0x3c  ))
#define IIC_CLR_INTR		((volatile int *)(IIC_BASE+0x40  ))
#define IIC_CLR_RX_UNDER		((volatile int *)(IIC_BASE+0x44  ))
#define IIC_CLR_RX_OVER		((volatile int *)(IIC_BASE+0x48  ))
#define IIC_CLR_TX_OVER		((volatile int *)(IIC_BASE+0x4c  ))
#define IIC_CLR_RD_REQ		((volatile int *)(IIC_BASE+0x50  ))
#define IIC_CLR_TX_ABRT		((volatile int *)(IIC_BASE+0x54  ))
#define IIC_CLR_RX_DONE		((volatile int *)(IIC_BASE+0x58  ))
#define IIC_CLR_ACTIVE		((volatile int *)(IIC_BASE+0x5c  ))
#define IIC_CLR_STOP_DET	((volatile int *)(IIC_BASE+0x60  ))
#define IIC_CLR_START_DET	((volatile int *)(IIC_BASE+0x64  ))
#define IIC_CLR_GEN_CALL	((volatile int *)(IIC_BASE+0x68  ))
#define IIC_ENABLE		((volatile int *)(IIC_BASE+0x6c  ))
#define IIC_STATUS		((volatile int *)(IIC_BASE+0x70  ))
#define IIC_TXFLR		((volatile int *)(IIC_BASE+0x74  ))
#define IIC_RXFLR		((volatile int *)(IIC_BASE+0x78  ))
#define IIC_SRESET		((volatile int *)(IIC_BASE+0x7c  ))
#define IIC_TX_ABRT_SOURCE		((volatile int *)(IIC_BASE+0x80  ))
#define IIC_VERSION_ID			((volatile int *)(IIC_BASE+0x84  ))


// Confiture Value
#ifndef IC_HC_COUNT_VALUES
#define IC_HC_COUNT_VALUES	0
#endif

#ifndef TX_ABW
#define TX_ABW
#endif

//Register Access Implementation

#define SET_REG(Reg ,data)  *Reg = (data)
#define I2C_ERROR(ErrorStr)	{printf("I2C:%s \n",ErrorStr) ; exit(1);}
/* If the register is R/W , then the following 
** rules will be applied to the named Macro.
** I2C_*** means set the register value 
** I2CR_*** means read the register value */

#define I2C_CON(data)			SET_REG(IIC_CON, (data)&0x007f)
#define I2CR_CON				((*IIC_CON)&0x007f)
#define I2C_TAR(data)			SET_REG(IIC_TAR, (data)&0x0fff)
#define I2CR_TAR				((*IIC_TAR)&0x0fff)
#define I2C_SAR(data)			SET_REG(IIC_SAR, (data)&0x03ff)
#define I2CR_SAR				((*IIC_SAR)&0x03ff)
#define I2C_HS_MADDR(data)		SET_REG(IIC_HS_MADDR, (data)&0x0007)
#define I2CR_HS_MADDR			((*IIC_HS_MADDR)&0x0007)
#define I2C_WRITE(data)			SET_REG(IIC_DATA_CMD, (data)&0x001ff)
#define I2C_READ				((*IIC_DATA_CMD)&0x001ff)

#if  IC_HC_COUNT_VALUES
#define I2C_SS_HCNT(data)		I2C_ERROR("Now SS_CLK_HCNT is ReadOnly.")
#define I2C_SS_LCNT(data)		I2C_ERROR("Now SS_CLK_LCNT is ReadOnly.")
#define I2C_FS_HCNT(data)		I2C_ERROR("Now FS_CLK_HCNT is ReadOnly.")
#define I2C_FS_LCNT(data)		I2C_ERROR("Now FS_CLK_LCNT is ReadOnly.")
#define I2C_HS_HCNT(data)		I2C_ERROR("Now HS_CLK_HCNT is ReadOnly.")
#define I2C_HS_LCNT(data)		I2C_ERROR("Now HS_CLK_LCNT is ReadOnly.")
#else
#define I2C_SS_HCNT(data)		SET_REG(IIC_SS_HCNT, data&0xffff)
#define I2C_SS_LCNT(data)		SET_REG(IIC_SS_LCNT, data&0xffff)
#define I2C_FS_HCNT(data)		SET_REG(IIC_FS_HCNT, data&0xffff)
#define I2C_FS_LCNT(data)		SET_REG(IIC_FS_LCNT, data&0xffff)
#define I2C_HS_HCNT(data)		SET_REG(IIC_HS_HCNT, data&0xffff)
#define I2C_HS_LCNT(data)	    SET_REG(IIC_HS_LCNT, data&0xffff)
#endif 

#define I2CR_SS_HCNT			((*IIC_SS_HCNT)&0xffff)
#define I2CR_SS_LCNT			((*IIC_SS_LCNT)&0xffff)
#define I2CR_FS_HCNT			((*IIC_FS_HCNT)&0xffff)
#define I2CR_FS_LCNT			((*IIC_FS_LCNT)&0xffff)
#define I2CR_HS_HCNT			((*IIC_HS_HCNT)&0xffff)
#define I2CR_HS_LCNT			((*IIC_HS_LCNT)&0xffff)
#define I2C_RAW_INTR_STAT		((*IIC_RAW_INTR_STAT)&0x0fff)
#define I2C_INTR_MASK(data)		SET_REG(IIC_INTR_MASK,data&0x0fff)
#define I2CR_INTR_MASK			((*IIC_INTR_MASK)&0x0fff)
#define I2C_INTR_STAT			((*IIC_INTR_STAT)&0x0fff)
#define I2C_RX_TL(data)			SET_REG(IIC_RX_TL, data&0x00ff)
#define I2CR_RX_TL				((*IIC_RX_TL)&0x00ff)
#define I2C_TX_TL(data)			SET_REG(IIC_TX_TL, data&0x00ff)
#define I2CR_TX_TL				((*IIC_TX_TL)&0x00ff)
#define I2C_CLR_INTR			((*IIC_CLR_INTR)&0x0001)
#define I2C_CLR_RX_UNDER		((*IIC_CLR_RX_UNDER)&0x0001)
#define I2C_CLR_RX_OVER			((*IIC_CLR_RX_OVER)&0x0001)
#define I2C_CLR_TX_OVER			((*IIC_CLR_TX_OVER)&0x0001)
#define I2C_CLR_RD_REQ			((*IIC_CLR_RD_REQ)&0x0001)
#define I2C_CLR_TX_ABRT			((*IIC_CLR_TX_ABRT)&0x0001)
#define I2C_CLR_RX_DONE			((*IIC_CLR_RX_DONE)&0x0001)
#define I2C_CLR_ACTIVITY		((*IIC_CLR_ACTIVITY)&0x0001)
#define I2C_CLR_STOP_DET		((*IIC_CLR_STOP_DET)&0x0001)
#define I2C_CLR_START_DET		((*IIC_CLR_START_DET)&0x0001)
#define I2C_CLR_GEN_CALL		((*IIC_CLR_GEN_CALL)&0x0001)

#define I2C_DISABLE				SET_REG(IIC_ENABLE ,0x0000)
#define I2C_ENABLE				SET_REG(IIC_ENABLE ,0x0001)
#define I2C_STATUS				((*IIC_STATUS)&0x001f)
#define I2C_TXFLR				((*IIC_TXFLR))
#define I2C_RXFLR				((*IIC_RXFLR))
#define I2C_SRESET(data)		SET_REG(IIC_SRESET,data&0x00000007)
#define I2C_TX_ABRT_SOURCE(data)	SET_REG(IIC_TX_ABRT_SOURCE,data&0x0000ffff)
#define I2CR_TX_ABRT_SOURCE		((*IIC_TX_ABRT_SOURCE)&0x0000ffff)
#define I2C_VERSION_ID			((*IIC_VERSION_ID))

// the followings are the Register bits.

/* State Register bit*/
#define RFF			0x0010
#define RFNE		0x0008
#define TFE			0x0004
#define TFNF		0x0002
#define sACTIVITY	0x0001

//end of Register bits

/* This struct aims at translate parameters.
** Para : addr , the slave's address
** Para : control, the control register's value
** Para : mask, the mask for interrupt
** Para : rx , the recive FIFO's depth
** Para : tx , the transmit FIFO's depth 
**/
typedef struct InitInfor{
	unsigned short addr;
	unsigned short control;
	unsigned short mask;
	unsigned short rx;
	unsigned short tx;
} INITINFOR;

/* This struct describe the SCL Paramter 
** mode : this is the I2C translate mode , such as SS =  , FS , HS
** hcnt : this is the High period for the SCL
** lcnt : this is the Low period for the SCL
**/
typedef enum {I2C_SS=1, I2C_FS, I2C_HS} I2CMODE ;

typedef struct SclValue{
	I2CMODE   mode;
	unsigned short hcnt;
	unsigned short lcnt;
}SCLVALUE;

typedef enum {false=0 , true=1} bool;


/* end of Register definition*/

#endif