detector.vhd

来自「FPGA数字电子系统设计与开发实例导航(源程序)」· VHDL 代码 · 共 42 行

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use WORK.UART_PACKAGE.ALL;
-- 实体声明
entity detector is
	port (
	clk : in std_logic;
	reset_n : in std_logic;
	RxD : in std_logic;
	new_data : out std_logic );
end detector;

--}} End of automatically maintained section
-- 结构体
architecture detector of detector is

-- 信号监测器状态机
signal state : dt_state;

begin
	-- enter your statements here --
	-- 主过程
	main : process(reset_n, clk)
	begin
		-- 复位信号
		if reset_n = '0' then
			state <= dt_unlock;
			new_data <= '0';
		elsif rising_edge(clk) then
			-- 检查输入信号和状态，当输入为低并且不在锁定状态时，输出new_data信号 
			if state = dt_unlock and RxD = '0' then
				new_data <= '1';
				state <= dt_lock;
			else
				new_data <= '0';
			end if;
		end if;
			
	end process;

end detector;