_primary.vhd

来自「FPGA数字电子系统设计与开发实例导航(源程序)」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity can_ibo is
    port(
        di              : in     vl_logic_vector(7 downto 0);
        do              : out    vl_logic_vector(7 downto 0)
    );
end can_ibo;