_primary.vhd

来自「FPGA数字电子系统设计与开发实例导航(源程序)」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity can_top is
    generic(
        tp              : integer := 1
    );
    port(
        rst_i           : in     vl_logic;
        ale_i           : in     vl_logic;
        rd_i            : in     vl_logic;
        wr_i            : in     vl_logic;
        port_0_io       : inout  vl_logic_vector(7 downto 0);
        cs_can_i        : in     vl_logic;
        clk_i           : in     vl_logic;
        rx_i            : in     vl_logic;
        tx_o            : out    vl_logic;
        irq_on          : out    vl_logic;
        clkout_o        : out    vl_logic
    );
end can_top;