_primary.vhd

来自「FPGA数字电子系统设计与开发实例导航(源程序)」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity can_crc is
    generic(
        tp              : integer := 1
    );
    port(
        clk             : in     vl_logic;
        data            : in     vl_logic;
        enable          : in     vl_logic;
        initialize      : in     vl_logic;
        crc             : out    vl_logic_vector(14 downto 0)
    );
end can_crc;