signal_gene.map.smsg

powerbuild学习重要资料 请下载

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 01:01:21 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signal_gene -c signal_gene
Info: Found 1 design units, including 1 entities, in source file datarom.v
    Info: Found entity 1: datarom
Info: Found 1 design units, including 1 entities, in source file signal_gene.v
    Info: Found entity 1: signal_gene
Info: Elaborating entity "signal_gene" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at signal_gene.v(21): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(25): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(38): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(42): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(56): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(60): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(74): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(78): truncated value with size 32 to match size of target (8)
Warning (10034): Output port "q_out[7]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[6]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[5]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[4]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[3]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[2]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[1]" at signal_gene.v(3) has no driver
Warning (10034): Output port "q_out[0]" at signal_gene.v(3) has no driver
Info: Elaborating entity "datarom" for hierarchy "datarom:datarom_component"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf
    Info: Found entity 1: lpm_rom
Info: Elaborating entity "lpm_rom" for hierarchy "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Elaborated megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom"
Info: Elaborated megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom", which is child of megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Instantiated megafunction "datarom:datarom_component|lpm_rom:lpm_rom_component" with the following parameter:
    Info: Parameter "intended_device_family" = "ACEX1K"
    Info: Parameter "lpm_address_control" = "REGISTERED"
    Info: Parameter "lpm_file" = "signal_gene.mif"
    Info: Parameter "lpm_outdata" = "UNREGISTERED"
    Info: Parameter "lpm_type" = "LPM_ROM"
    Info: Parameter "lpm_width" = "8"
    Info: Parameter "lpm_widthad" = "9"
Error: Port "q_out" does not exist in macrofunction "datarom_component" File: E:/HDL project/signal_gene/signal_gene.v Line: 11
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 16 warnings
    Info: Allocated 120 megabytes of memory during processing
    Error: Processing ended: Tue Dec 30 01:01:22 2008
    Error: Elapsed time: 00:00:01